Results 101 to 110 of about 4,503 (162)
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The Integration VLSI Journal, 1998
Summary: An increasing part of microelectronic systems is implemented on the basis of predesigned and preverified modules, so-called cores, which are reused in many instances. Core-providers offer RISC-kernels, embedded memories, DSPs, and many other functions, and built-in self-test is the appropriate method for testing complex systems composed of ...
Hans-Joachim Wunderlich
exaly +3 more sources
Summary: An increasing part of microelectronic systems is implemented on the basis of predesigned and preverified modules, so-called cores, which are reused in many instances. Core-providers offer RISC-kernels, embedded memories, DSPs, and many other functions, and built-in self-test is the appropriate method for testing complex systems composed of ...
Hans-Joachim Wunderlich
exaly +3 more sources
Theory of transparent BIST for RAMs
IEEE Transactions on Computers, 1996Summary: I present the theoretical aspects of a technique called transparent BIST for RAMs. This technique applies to any RAM test algorithm and transforms it into a transparent one. The interest of the transparent test algorithms is that testing preserves the contents of the RAM.
Michael Nicolaidis
exaly +3 more sources
Online BIST and BIST-based diagnosis of FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004We present the first online built-in self-test (BIST) and BIST-based diagnosis of programmable logic resources in field-programmable gate arrays (FPGAs). These techniques were implemented and used in a roving self-testing areas (STARs) approach to testing and reconfiguration of FPGAs for fault-tolerant applications.
M Abramovici
exaly +2 more sources
A tool for automatic generation of BISTed and transparent BISTed RAMs
Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors, 2003An efficient BIST architecture for RAMs that is based on M. Marinescu's (1982) algorithm is presented. This architecture considers the different levels of hierarchy of the algorithm and uses a block to implement each level of this hierarchy. Efficient implementations for these blocks are given.
O. Kebichi, Michael Nicolaidis
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Segment Weighted Random BIST (SWR-BIST): A Low Power BIST Technique
2005 IEEE Asian Solid-State Circuits Conference, 2005This paper presents a segment weighted random built-in self test (SWR-BIST) technique for low power testing. This technique divides the scan chain into segments of different weights. Heavily weighted segments have more biased probability than lightly weighted segments.
Chun-yi Lee, Chien-mo Li
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Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference, 2002
The authors show how to combine a conventional built-in self-test method with a simple method for online error detection for combinational circuits. The output sequence of one or more components of the signature analyzer is monitored, in test mode, by an error detection circuit consisting of a one-cover and a zero-cover.
Michael Gössel, Helmut Jürgensen
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The authors show how to combine a conventional built-in self-test method with a simple method for online error detection for combinational circuits. The output sequence of one or more components of the signature analyzer is monitored, in test mode, by an error detection circuit consisting of a one-cover and a zero-cover.
Michael Gössel, Helmut Jürgensen
openaire +1 more source
Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005
This paper presents a new reseeding technique that considerably reduces the storage required for the seeds as well as the test application time by alternating between ATPG and reseeding to optimize the seed selection. The technique avoids loading a new seed into the PRPG whenever the PRPG can be placed in a state that generates test patterns without ...
Ahmad A. Al-Yamani, Edward J. McCluskey
openaire +1 more source
This paper presents a new reseeding technique that considerably reduces the storage required for the seeds as well as the test application time by alternating between ATPG and reseeding to optimize the seed selection. The technique avoids loading a new seed into the PRPG whenever the PRPG can be placed in a state that generates test patterns without ...
Ahmad A. Al-Yamani, Edward J. McCluskey
openaire +1 more source
IEEE International Conference on Test, 2005., 2006
In modern SoCs embedded memories include the large majority of defects. In addition defect types are becoming more complex and diverse and may escape detection during fabrication test. As a matter of fact memories have to be tested by test algorithms achieving very high fault coverage.
Slimane Boutobza +3 more
openaire +1 more source
In modern SoCs embedded memories include the large majority of defects. In addition defect types are becoming more complex and diverse and may escape detection during fabrication test. As a matter of fact memories have to be tested by test algorithms achieving very high fault coverage.
Slimane Boutobza +3 more
openaire +1 more source
Deterministic BIST with Partial Scan
Journal of Electronic Testing, 2000An efficiency deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum number of flip-flops to be scannable so that the remaining circuit has a pipeline-like structure.
Kiefer, Gundolf +1 more
openaire +2 more sources