Results 121 to 130 of about 4,503 (162)
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TI-BIST: a temperature independent analog BIST for switched-capacitor filters
Proceedings of the Ninth Asian Test Symposium, 2002This paper describes a method to obtain a temperature independent analog BIST. The test procedure is based on the reuse of existing analog circuits, configured either as stimuli generators or as signature analyzers. The paper explains the general problem of temperature deviation present in analog BIST, and shows an approach to overcome this limitation,
Luigi Carro +5 more
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TAO-BIST: a framework for testability analysis and optimization of RTL circuits for BIST
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), 2003In this paper, we present TAO-BIST, a framework for testing register-transfer level (RTL) controller-datapath circuits using built-in self-test (BIST). Conventional BIST techniques at the RTL generally introduce more testability hardware than is necessary, thereby causing unnecessary area, delay and power overheads.
Srivaths Ravi 0001 +2 more
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E-BIST: enhanced test-per-clock BIST architecture
IEE Proceedings - Computers and Digital Techniques, 2002A new enhanced built-in self-test (E-BIST) architecture, that is suitable for a test-per-clock scheme, is proposed. The E-BIST architecture is based on STUMPS (Self-Test Using MISR and Parallel Shift-register sequence generators), which uses a linear feedback shift register (LFSR) as the test generator, a multiple-input shift register (MISR) as the ...
Y. Son, J. Chong, G. Russell
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Retiming for BIST-sequential circuits
Proceedings of ISCAS'95 - International Symposium on Circuits and Systems, 2002Pseudoexhaustive BIST of sequential circuits consists of breaking all cycles in the circuit, partitioning the obtained acyclic circuit by placing some segmentation cells in the circuit, and balancing the partitioned circuit by introducing (or selecting in the scan path) additional flip-flops as delays in order to apply combinational TPG methods, In ...
Samir Lejmi +2 more
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Online BIST for embedded systems
IEEE Design & Test of Computers, 1998Embedded systems must meet increasingly high expectations of safety and high reliability. The authors survey online-testing techniques for identifying faults that can lead to system failure. They focus on online built-in self-test and its role in a comprehensive testing approach.
Hussain Al-Asaad +2 more
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Circular BIST with partial scan
International Test Conference 1988 Proceeding@m_New Frontiers in Testing, 2003A BIST (built-in self test) methodology that uses the circular BIST technique to perform a random test of sequential logic circuits is presented. The fault coverage obtained using this technique is supplemented by deterministic tests that are presented to the CUT (circuit under test) by configuring the circular path as a partial scan chain.
M. M. Pradhan +3 more
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Proceedings of International Conference on Computer Aided Design, 2002
Hans-Joachim Wunderlich, Gundolf Kiefer
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Hans-Joachim Wunderlich, Gundolf Kiefer
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Analysis of Relationship Between Bitcoin Prices and BIST 100, BIST Bank and BIST Technology Index
2020In this study, whether the Bitcoin currency, which has the highest volume in the market among crypto currencies, has a relationship between BIST 100, BIST Bank and BIST Technology index in the short and long term is examined using time series analysis methods.
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Shrinking wide compressors [BIST]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995Quite often built-in self-test (BIST) designs make use of multiple-input signature registers (MISR's) to compress the test data. Normally a MISR includes a stage for every signal that it is sampling. In some applications this leads to very wide MISR's that may include several hundred stages.
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