Results 141 to 150 of about 19,898 (183)
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Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference, 2002
The authors show how to combine a conventional built-in self-test method with a simple method for online error detection for combinational circuits. The output sequence of one or more components of the signature analyzer is monitored, in test mode, by an error detection circuit consisting of a one-cover and a zero-cover.
Michael Gössel, Helmut Jürgensen
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The authors show how to combine a conventional built-in self-test method with a simple method for online error detection for combinational circuits. The output sequence of one or more components of the signature analyzer is monitored, in test mode, by an error detection circuit consisting of a one-cover and a zero-cover.
Michael Gössel, Helmut Jürgensen
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Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005
This paper presents a new reseeding technique that considerably reduces the storage required for the seeds as well as the test application time by alternating between ATPG and reseeding to optimize the seed selection. The technique avoids loading a new seed into the PRPG whenever the PRPG can be placed in a state that generates test patterns without ...
Ahmad A. Al-Yamani, Edward J. McCluskey
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This paper presents a new reseeding technique that considerably reduces the storage required for the seeds as well as the test application time by alternating between ATPG and reseeding to optimize the seed selection. The technique avoids loading a new seed into the PRPG whenever the PRPG can be placed in a state that generates test patterns without ...
Ahmad A. Al-Yamani, Edward J. McCluskey
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IEEE International Conference on Test, 2005., 2006
In modern SoCs embedded memories include the large majority of defects. In addition defect types are becoming more complex and diverse and may escape detection during fabrication test. As a matter of fact memories have to be tested by test algorithms achieving very high fault coverage.
Slimane Boutobza +3 more
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In modern SoCs embedded memories include the large majority of defects. In addition defect types are becoming more complex and diverse and may escape detection during fabrication test. As a matter of fact memories have to be tested by test algorithms achieving very high fault coverage.
Slimane Boutobza +3 more
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2004
This paper addresses the problem of Test Effectiveness (TE) evaluation of digital circuits implemented in FPGAs. A Hardware Fault Simulation (HFS) technique, particularly useful for evaluating the effectiveness of built-in self-test (BIST) is detailed.
Abilio Parreira +2 more
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This paper addresses the problem of Test Effectiveness (TE) evaluation of digital circuits implemented in FPGAs. A Hardware Fault Simulation (HFS) technique, particularly useful for evaluating the effectiveness of built-in self-test (BIST) is detailed.
Abilio Parreira +2 more
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Deterministic BIST with Partial Scan
Journal of Electronic Testing, 2000An efficiency deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum number of flip-flops to be scannable so that the remaining circuit has a pipeline-like structure.
Kiefer, Gundolf +1 more
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Online BIST and BIST-based diagnosis of FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004We present the first online built-in self-test (BIST) and BIST-based diagnosis of programmable logic resources in field-programmable gate arrays (FPGAs). These techniques were implemented and used in a roving self-testing areas (STARs) approach to testing and reconfiguration of FPGAs for fault-tolerant applications.
Miron Abramovici +2 more
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An on-chip ADC BIST solution and the BIST enabled calibration scheme
2017 IEEE International Test Conference (ITC), 2017This paper presents a complete on-chip ADC BIST solution based on a segmented stimulus error identification algorithm known as USER-SMILE. By adapting the algorithm for efficient hardware realization, the solution is implemented towards a 1Msps 12-bit SAR ADC on a 28nm CMOS automotive microcontroller. While sufficient test accuracy is demonstrated, the
Xiankun Jin +7 more
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HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs
International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), 2003This paper proposes HD-BIST, a complete framework to support the definition of the scheduling strategy and mechanism of the BISTed blocks of a complex system. Three different layers are presented, to define the HD-BIST approach in terms of a set of high-level BIST scheduling primitives, a communication protocol, and a possible hardware implementation ...
BENSO, Alfredo +4 more
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Versatile BIST: an integrated approach to on-line/off-line BIST
Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), 2002In this paper we report a versatile BIST approach (VBIST) that targets both off-line and on-line self test. VBIST uses off-line BIST circuitry for on-line testing as well. Unlike traditional on-line self test approaches, VBIST does not use functional data as test inputs.
Ramesh Karri, Nilanjan Mukherjee
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Programmable BIST space compactors
IEEE Transactions on Computers, 1996Summary: We address test data compaction for built-in self-test (BIST). We propose a novel taxonomy useful for classifying and comparing BIST compactors. The taxonomy uses the following attributes: space, time, memory, linearity, and circuit (functional) specificity.
André Ivanov +2 more
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