Results 151 to 160 of about 19,898 (183)

BIST the hard way

IEEE Design and Test of Computers, 2005
Reviewed in this issue A Designer's Guide to Built-in Self-Test, by Charles E. Stroud (Springer, 2002, ISBN 1-402-07050-0, 344 pp., $125).
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Recent advances in BIST

Digest of Papers. 1992 IEEE VLSI Test Symposium, 2003
The author briefly reviews various recent results in data compression for BIST. His primary focus is on MISR compression, considering the practical design issues that interest a designer. Issues related to the choice of error model, feedback polynomial, and suitable test lengths are discussed. >
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BIST for systems-on-a-chip

Integration, 1998
Summary: An increasing part of microelectronic systems is implemented on the basis of predesigned and preverified modules, so-called cores, which are reused in many instances. Core-providers offer RISC-kernels, embedded memories, DSPs, and many other functions, and built-in self-test is the appropriate method for testing complex systems composed of ...
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Analyzing BIST robustness

Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002
Deals with the problem of fault detection and fault handling robustness in BIST schemes. In particular we analyze the susceptibility of signature analyzers to internal faults. Various fault models (black box) within the analyzer circuitry are taken into account.
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An universal BIST methodology for interconnects

1993 IEEE International Symposium on Circuits and Systems, 2002
A methodology for the design and implementation of an universal interconnect built-in self test module for boundary-scan-based interconnects is proposed. Such a methodology is able to test any interconnects without knowing their connection configuration in advance.
Chiyuan Chang, Chauchin Su
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Stop & go BIST

Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002), 2003
A BIST method enabling two-pattern testing at-speed without violating thermal constraints by introducing cool down periods is proposed. The application of the method is demonstrated based on a scalable BIST architecture. Applicability on IP cores is given since only a two-pattern test set is required as input.
Ilia Polian, Bernd Becker 0001
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Theory of transparent BIST for RAMs

IEEE Transactions on Computers, 1996
Summary: I present the theoretical aspects of a technique called transparent BIST for RAMs. This technique applies to any RAM test algorithm and transforms it into a transparent one. The interest of the transparent test algorithms is that testing preserves the contents of the RAM.
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TI-BIST: a temperature independent analog BIST for switched-capacitor filters

Proceedings of the Ninth Asian Test Symposium, 2002
This paper describes a method to obtain a temperature independent analog BIST. The test procedure is based on the reuse of existing analog circuits, configured either as stimuli generators or as signature analyzers. The paper explains the general problem of temperature deviation present in analog BIST, and shows an approach to overcome this limitation,
Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell   +5 more
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TAO-BIST: a framework for testability analysis and optimization of RTL circuits for BIST

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), 2003
In this paper, we present TAO-BIST, a framework for testing register-transfer level (RTL) controller-datapath circuits using built-in self-test (BIST). Conventional BIST techniques at the RTL generally introduce more testability hardware than is necessary, thereby causing unnecessary area, delay and power overheads.
Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha   +2 more
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Accumulator based deterministic BIST

Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), 2002
Most built-in self test (BIST) solutions require specialized test pattern generation hardware which may introduce significant area overhead and performance degradation. Recently, some authors proposed test pattern generation on chip by means of functional units also used in system mode like adders or multipliers. These schemes generate pseudo-random or
Rainer Dorsch, Hans-Joachim Wunderlich
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