Results 111 to 120 of about 4,503 (162)

An on-chip ADC BIST solution and the BIST enabled calibration scheme

2017 IEEE International Test Conference (ITC), 2017
This paper presents a complete on-chip ADC BIST solution based on a segmented stimulus error identification algorithm known as USER-SMILE. By adapting the algorithm for efficient hardware realization, the solution is implemented towards a 1Msps 12-bit SAR ADC on a 28nm CMOS automotive microcontroller. While sufficient test accuracy is demonstrated, the
Xiankun Jin, Tao Chen 0006, Mayank Jain, Arun Kumar Barman, David Kramer, Doug Garrity, Randall L. Geiger, Degang Chen 0001   +7 more
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FPGAs BIST Evaluation

2004
This paper addresses the problem of Test Effectiveness (TE) evaluation of digital circuits implemented in FPGAs. A Hardware Fault Simulation (HFS) technique, particularly useful for evaluating the effectiveness of built-in self-test (BIST) is detailed.
Abilio Parreira, João Paulo Teixeira 0001, Marcelino B. Santos   +2 more
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Versatile BIST: an integrated approach to on-line/off-line BIST

Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), 2002
In this paper we report a versatile BIST approach (VBIST) that targets both off-line and on-line self test. VBIST uses off-line BIST circuitry for on-line testing as well. Unlike traditional on-line self test approaches, VBIST does not use functional data as test inputs.
Ramesh Karri, Nilanjan Mukherjee
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Recent advances in BIST

Digest of Papers. 1992 IEEE VLSI Test Symposium, 2003
The author briefly reviews various recent results in data compression for BIST. His primary focus is on MISR compression, considering the practical design issues that interest a designer. Issues related to the choice of error model, feedback polynomial, and suitable test lengths are discussed. >
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HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), 2003
This paper proposes HD-BIST, a complete framework to support the definition of the scheduling strategy and mechanism of the BISTed blocks of a complex system. Three different layers are presented, to define the HD-BIST approach in terms of a set of high-level BIST scheduling primitives, a communication protocol, and a possible hardware implementation ...
BENSO, Alfredo, CATALDO S., CHIUSANO, SILVIA ANNA, PRINETTO, Paolo Ernesto, ZORIAN Y.   +4 more
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BIST the hard way

IEEE Design and Test of Computers, 2005
Reviewed in this issue A Designer's Guide to Built-in Self-Test, by Charles E. Stroud (Springer, 2002, ISBN 1-402-07050-0, 344 pp., $125).
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Programmable BIST space compactors

IEEE Transactions on Computers, 1996
Summary: We address test data compaction for built-in self-test (BIST). We propose a novel taxonomy useful for classifying and comparing BIST compactors. The taxonomy uses the following attributes: space, time, memory, linearity, and circuit (functional) specificity.
André Ivanov, Barry K. Tsuji, Yervant Zorian   +2 more
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An universal BIST methodology for interconnects

1993 IEEE International Symposium on Circuits and Systems, 2002
A methodology for the design and implementation of an universal interconnect built-in self test module for boundary-scan-based interconnects is proposed. Such a methodology is able to test any interconnects without knowing their connection configuration in advance.
Chiyuan Chang, Chauchin Su
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Analyzing BIST robustness

Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002
Deals with the problem of fault detection and fault handling robustness in BIST schemes. In particular we analyze the susceptibility of signature analyzers to internal faults. Various fault models (black box) within the analyzer circuitry are taken into account.
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Stop & go BIST

Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002), 2003
A BIST method enabling two-pattern testing at-speed without violating thermal constraints by introducing cool down periods is proposed. The application of the method is demonstrated based on a scalable BIST architecture. Applicability on IP cores is given since only a two-pattern test set is required as input.
Ilia Polian, Bernd Becker 0001
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