Results 141 to 150 of about 18,840,038 (173)

13.2 A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V

IEEE International Solid-State Circuits Conference, 2019
A resistive RAM (ReRAM) macro is developed as a low-cost, magnetic-disturb-immune option for embedded, non-volatile memory for SoCs used in IoT and automotive applications.
P. Jain, U. Arslan, M. Sekhar, Blake C. Lin, Liqiong Wei, Tanay Sahu, Juan Alzate-vinasco, Ajay Vangapaty, Mesut Meterelliyoz, N. Strutt, Albert B. Chen, P. Hentges, Pedro A. Quintero, C. Connor, O. Golonzka, K. Fischer, F. Hamzaoglu   +16 more
semanticscholar   +1 more source

A 12-bit 10GS/s Time-Interleaved SAR ADC with Even/Odd Channel-Correlated Absolute Error-Based Over-Nyquist Timing-Skew Calibration in 5nm FinFET

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
This paper presents an over-Nyquist 12-bit 10GS/s time-interleaved (TI) ADC with a background timing-skew calibration. An absolute error-based auto-correlation algorithm enables calibration of time skew for both the first and second Nyquist inputs, while
Junsang Park, Jinwoo Park, Jaemin Hong, Sun-Jae Park, Dongsuk Lee, Sungno Lee, Hyochul Shin, Kyung-Hoon Lee, Byeongwoo Koo, Youngjae Cho, Michael Choi, Jongshin Shin   +11 more
semanticscholar   +1 more source

Interpretable Neural Network to Model and to Reduce Self-Heating of FinFET Circuitry

2020 IEEE Symposium on VLSI Technology, 2020
An interpretable neural network (NN) is used to model the self-heating (SH) in complex FinFET circuits. The NN training/testing datasets from 3 -stage to 37 -stage chain circuits in folded layout composed of inverter (INV)/NAND/NOR are simulated by our ...
Chia-Che Chung, Hsin-Cheng Lin, H. H. Lin, W. K. Wan, M. Yang, C. Liu   +5 more
semanticscholar   +1 more source

A 1 V Bandgap Reference in 7-nm FinFET with a Programmable Temperature Coefficient and an Inaccuracy of ±0.2% from −45°C to 125°C

European Solid-State Circuits Conference, 2018
A 1-V precision voltage reference in 7-nm FinFET CMOS is presented. It allows to control a temperature coefficient of the generated voltage. Proposed trim techniques, favored for short test times, help to achieve good accuracy in spite of the challenges ...
Umanath Kamath, Edward Cullen, J. Jennings, Ionut Cical, Darragh Walsh, P. Lim, B. Farley, R. B. Staszewski   +7 more
semanticscholar   +1 more source

Single-Event Latchup in a 7-nm Bulk FinFET Technology

IEEE Transactions on Nuclear Science, 2021
Terrestrial neutron and alpha particle irradiation data for a 7-nm bulk FinFET technology reveal the persisting reliability threat single-event latchup (SEL) poses to advanced technology nodes.
D. Ball, C. B. Sheets, L. Xu, J. Cao, S. Wen, R. Fung, C. Cazzaniga, J. Kauppila, L. Massengill, B. Bhuva   +9 more
semanticscholar   +1 more source

Localization of Subtle Front-End FinFET Defects Using EBIC

International Symposium for Testing and Failure Analysis
We demonstrate the effectiveness of combining top-down and cross-sectional electron beam induced current (EBIC) imaging with SEM nanoprobe analysis to identify subtle front-end defects in advanced FinFET technology.
Nick Pronin, K. Ly, Tony Chrastecky, Jacob Levenson, Eric Yi, Kris Dickson, Sam Subramanian, Keith A. Serrels   +7 more
semanticscholar   +1 more source

A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

IEEE Journal of Solid-State Circuits
A 3-nm FinFET single-port (SP) 6T SRAM macro is proposed that utilizes a far-end pre-charge (FPC) circuit and weak-bit (WB) tracking circuit. These circuits can decrease write cycle time by decreasing the pre-charge period and engaging read cycle time by
Yumito Aoyagi, Koji Nii, M. Yabuuchi, Tomotaka Tanaka, Y. Ishii, Yoshiaki Osada, Takaaki Nakazato, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, H. Liao, Tsung-Yung Jonathan Chang   +11 more
semanticscholar   +1 more source

A 20 GHz 8-bit All-N-Transistor Logic CLA Using 16-nm FinFET Technology

Asia Pacific Conference on Circuits and Systems, 2021
This paper presents a 20 GHz 8-bit carry-lookahead adder (CLA) using all-N-transistor (ANT) logic. By using the proposed ANT logic, an auxiliary current path through NMOS transistor is provided such that the speed limitation caused by PMOS is avoided ...
Tzung-Je Lee, Wen-Shou Yang, Chua-Chin Wang   +2 more
semanticscholar   +1 more source

MRAM as Embedded Non-Volatile Memory Solution for 22FFL FinFET Technology

International Electron Devices Meeting, 2018
This paper presents key features of MRAM-based non-volatile memory embedded into Intel 22FFL technology. 22FFL is a high performance, ultra low power FinFET technology for mobile and RF applications with extensive high voltage and analog support, and a ...
O. Golonzka, J. G. Alzate, U. Arslan, M. Bohr, P. Bai, S. BrockmanJustin, Buford Benjamin, C. Connor, N. Das, B. Doyle, T. Ghani, F. Hamzaoglu, P. Heil, P. Hentges, R. Jahan, D. Kencke, Blake C. Lin, M. Lu, M. Mainuddin, Mesut Meterelliyoz, P. Nguyen, D. Nikonov, P. O'brienKevin, J. O. Donnell, K. Oguz, G. OuelletteDaniel, Joodong Park, J. Pellegren, C. Puls, Pedro A. Quintero, T. Rahman, A. Romang, M. Sekhar, A. Selarka, M. Seth, A. J. Smith, A. Smith, Liqiong Wei, C. Wiegand, Z. Zhang, K. Fischer   +40 more
semanticscholar   +1 more source

Novel Concept of Hardware Security in Using Gate-switching FinFET Nonvolatile Memory to Implement True-Random-Number Generator

International Electron Devices Meeting, 2020
For the first time, we use a gate-switching resistance memory to implement the TRNG (True random number generator). First, a resistance memory was built on a FinFET platform, named RG-FinFET(resistive-gate) RRAM which was simply an MIM(metal-insulator ...
W. Yang, B. Y. Chen, C. Chuang, E. Hsieh, K. S. Li, S. Chung   +5 more
semanticscholar   +1 more source