Results 121 to 130 of about 19,628,440 (150)

Anisotropic exchange interaction of two hole-spin qubits. [PDF]

Nat Phys
Geyer S, Hetényi B, Bosco S, Camenzind LC, Eggli RS, Fuhrer A, Loss D, Warburton RJ, Zumbühl DM, Kuhlmann AV.   +9 more
europepmc   +1 more source

Design and analysis of high-k wrapped underlap induced GaN multi-channel GAA nanosheet FET for enhanced performance with cut-off frequency in THz range. [PDF]

Sci Rep
Singh S, Dhar RS, Banerjee A, Gupta V.
europepmc   +1 more source

Energy-constrained workflow scheduling for DVFS-enabled heterogeneous systems in cloud computing environments. [PDF]

Sci Rep
Ahmad W, Silaparasetti L, Arya P, Pandya S, Kumar P, Khan T, Alabdulatif A.   +6 more
europepmc   +1 more source

Resistive switching memristors: structures, materials, fabrication techniques, and process challenges for VLSI integration. [PDF]

RSC Adv
Singla R, Pant D, Nautiyal P, Painuly A.
europepmc   +1 more source

Highly Selective Isotropic Etching of Si to SiGe Using CF₄/O₂/N₂ Plasma for Advanced GAA Nanosheet Transistor. [PDF]

Nanomaterials (Basel)
Li J, Sun X, Huang Z, Zhang DW.
europepmc   +1 more source

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology. [PDF]

Nanomaterials (Basel)
Radamson HH, Miao Y, Zhou Z, Wu Z, Kong Z, Gao J, Yang H, Ren Y, Zhang Y, Shi J, Xiang J, Cui H, Lu B, Li J, Liu J, Lin H, Xu H, Li M, Cao J, He C, Duan X, Zhao X, Su J, Du Y, Yu J, Wu Y, Jiang M, Liang D, Li B, Dong Y, Wang G.   +30 more
europepmc   +1 more source

Ground Plane Fin-Shaped Field Effect Transistor (GP-FinFET): A FinFET for Low Leakage Power Circuits

Microelectronic Engineering, 2012
In this paper, a fin-shaped field effect transistor (FinFET) structure which uses ground plane concept is proposed and theoretically investigated. The ground plane reduces the coupling of electric field between the source and drain reducing drain-induced
Mehdi Saremi, Ali Afzali-Kusha, Saeed Mohammadi   +2 more
exaly   +2 more sources

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Improved digital performance of charge plasma based junctionless C-FinFETs at 10 nm technology node and beyond

AEU - International Journal of Electronics and Communications, 2020
Abstract This paper investigates the digital performance of novel charge plasma based complementary (CPJL) FinFET inverters in terms of low and high noise margins, logic swing LS, DC power consumption PDC, rise tr and fall tf times, and propagations delay at both 10 and 7 nm technology nodes. In addition, their performance is compared with equivalent
Kallolini Banerjee, Abhijit Biswas
openaire   +1 more source

Effects of Fin Height on Digital Performance of Hybrid p-Si/n-InGaAs C-FinFETs at 25 nm Gate Length

2020
We report effects of Fin height on the logic application of hybrid complementary FinFETs (HC-Fins) composed of n-FinFETs and p-FinFETs employing InGaAs and Si channel, respectively, at gate length of 25 nm. Using extensive numerical analysis, we calculate rise time tr and fall time tf of NAND gate based inverter built with HC-Fins.
Kallolini Banerjee, Abhijit Biswas
openaire   +1 more source