Results 41 to 50 of about 1,837,572 (294)
Distributed wireless network resource optimisation method based on mobile edge computing
IET Networks, EarlyView., 2022 This paper mainly compares the network ranking leader, consumption amount and network signal reception of the three algorithms. The study found that in terms of network sort captain, there are significant differences between the CPLEX algorithm, the CCST algorithm, and edge computing methods. The CCST algorithm and edge computing have little difference
Jiongting Jiang +4 more
wiley +1 more source
Gain-Aware Cache Replacement Strategy for RDD Data Blocks on Spark [PDF]
Jisuanji kexue yu tansuoCache replacement is a hot and difficult research topic in the field of memory optimization of Spark. However, the diversity of application characteristics, limited memory resources, and the uncertainty of cache replacement present challenges to achieve ...
HE Sha, TANG Xiaoyong
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Software-Level Memory Regulation to Reduce Execution Time Variation on Multicore Real-Time Systems
IEEE Access, 2022 Modern real-time embedded systems are equipped with multi-core processors to execute computationally intensive tasks. In multi-core architecture, last-level cache memory is shared by cores.
Sihyeong Park, Jemin Lee, Hyungshin Kim
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IET Networks, EarlyView., 2023 The topic discussed was the intelligent design of network multimedia using BD and virtual AI technology. First of all, the authors gave a brief overview of its relevant research background, and then comprehensively analysed the advantages and disadvantages of previous scholars' research on network multimedia.
Xin Zhang
wiley +1 more source
Cache Coherence Protocol Design and Simulation Using IES (Invalid Exclusive read/write Shared) State
مجلة بغداد للعلوم, 2017 To improve the efficiency of a processor in recent multiprocessor systems to deal with data, cache memories are used to access data instead of main memory which reduces the latency of delay time.
Baghdad Science Journal
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Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs
IEEE Access, 2022 Designs implemented on field-programmable gate arrays (FPGAs) via high-level synthesis (HLS) suffer from off-chip memory latency and bandwidth bottlenecks. FPGAs can access both large but slow off-chip memories (DRAM), and fast but small on-chip memories
Giovanni Brignone +3 more
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Evaluating a number of cache coherency misses based on a statistical model
Труды Института системного программирования РАН, 2018 False cache sharing happens when different parallel execution threads update the variables that reside in the same cache line. We suggest in this paper to evaluate the number of cache misses using code instrumentation and post-mortem trace analysis: the ...
Evgeny Velesevich
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Striping Input Feature Map Cache for Reducing off-chip Memory Traffic in CNN Accelerators
Telfor Journal, 2020 Data movement between the Convolutional Neural Network (CNN) accelerators and off-chip memory is critical concerning the overall power consumption. Minimizing power consumption is particularly important for low power embedded applications.
R. Struharik, V. Vranjkovic
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Benchmarking the cache memory effect
, 1996 A new performance model of the memory hierarchy is first introduced, which describes all possible scenarios for the calculation process, including the important case when the cache memory is bypassed. A detailed study of each scenario is then given along
Getov, Vladimir
core +1 more source
Advanced Engineering Materials, EarlyView.Digitalizing electroplating requires both domain knowledge and interoperability. This work introduces PlatOn, a domain ontology for trivalent chromium plating and coating characterization, and a hybrid pipeline that aligns it to a mid‐level reference ontology by combining eight similarity metrics with language model reasoning. Expert‐validated mappings
Janik Harter +10 more
wiley +1 more source