Results 21 to 30 of about 132,994 (259)
Micromachines, 2022 In an asymmetric multi-core architecture, multiple heterogeneous cores share the last-level cache (LLC). Due to the different memory access requirements among heterogeneous cores, the LLC competition is more intense.
Juan Fang +4 more
doaj +1 more source
IET Communications, EarlyView., 2022 Abstract The goal of this work is to investigate how the self‐awareness characteristic of autonomic computing, paired with existing performance optimization rules, may be used in applications to minimise multi‐core processor performance concerns. The suggested self‐awareness technique can assist applications in self‐execution while also assisting other
Surendra Kumar Shukla +8 more
wiley +1 more source
An Effective Burst Access Scheme for Lossless Frame Buffer Compression on a Video Decoder
IEEE Access, 2021 For decoding high-resolution image stored in external memory after lossless compression, it is inevitable necessary to allow variable-length data types and this may decreases the efficiency in real time read of arbitrary compressed macro block without ...
Jaeshin Lee +4 more
doaj +1 more source
Cache-only memory architectures [PDF]
Computer, 1999 The shared memory concept makes it easier to write parallel programs, but tuning the application to reduce the impact of frequent long latency memory accesses still requires substantial programmer effort. Researchers have proposed using compilers, operating systems, or architectures to improve performance by allocating data close to the processors that
Fredrik Dahlgren, Josep Torrellas
openaire +1 more source
Precision planter monitoring system based on mobile communication network
IET Networks, EarlyView., 2022 Abstract Sowing is an important link in agricultural production and the basis for ensuring high yields and bumper harvests. Agriculture requires precision plows with good performance and stable work. However, the seeding process is in a completely closed state, and the operator relies mainly on experience to judge the operating state and performance of
Bing Li, Jiyun Li
wiley +1 more source
Intent Arabic text categorisation based on different machine learning and term frequency
IET Networks, EarlyView., 2022 Abstract The complexity of Internet network configurations has made managing networks a complicated undertaking. Intent‐Based Networking (IBN) is a potential solution to this issue. In contrast to conventional networks, where a concrete description of the settings typically conveys a network administrator's goal kept on each device, an administrator's ...
Mohammad Fadhil Mahdi +1 more
wiley +1 more source
Proposal New Cache Coherence Protocol to Optimize CPU Time through Simulation Caches [PDF]
Engineering and Technology Journal, 2016 The cache coherence is the most important issue that rapidly affected the performance of a multicore processor as a result of increasing the number of cores on chip multiprocessors and the shared memory program that will be run on these processors ...
Luma Fayeq Jalil +2 more
doaj +1 more source
Distributed wireless network resource optimisation method based on mobile edge computing
IET Networks, EarlyView., 2022 This paper mainly compares the network ranking leader, consumption amount and network signal reception of the three algorithms. The study found that in terms of network sort captain, there are significant differences between the CPLEX algorithm, the CCST algorithm, and edge computing methods. The CCST algorithm and edge computing have little difference
Jiongting Jiang +4 more
wiley +1 more source
Locality-Based Cache Management and Warp Scheduling for Reducing Cache Contention in GPU
Micromachines, 2021 GPGPUs has gradually become a mainstream acceleration component in high-performance computing. The long latency of memory operations is the bottleneck of GPU performance. In the GPU, multiple threads are divided into one warp for scheduling and execution.
Juan Fang, Zelin Wei, Huijing Yang
doaj +1 more source
HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems [PDF]
, 1968 Spin-Transfer Torque RAM (STT-RAM) is widely considered a promising alternative to SRAM in the memory hierarchy due to STT-RAM's non-volatility, low leakage power, high density, and fast read speed.
Adegbija, Tosiron, Kuan, Kyle
core +4 more sources