Results 21 to 30 of about 6,716 (257)
Proposal New Cache Coherence Protocol to Optimize CPU Time through Simulation Caches [PDF]
Engineering and Technology Journal, 2016 The cache coherence is the most important issue that rapidly affected the performance of a multicore processor as a result of increasing the number of cores on chip multiprocessors and the shared memory program that will be run on these processors ...
Luma Fayeq Jalil +2 more
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Locality-Based Cache Management and Warp Scheduling for Reducing Cache Contention in GPU
Micromachines, 2021 GPGPUs has gradually become a mainstream acceleration component in high-performance computing. The long latency of memory operations is the bottleneck of GPU performance. In the GPU, multiple threads are divided into one warp for scheduling and execution.
Juan Fang, Zelin Wei, Huijing Yang
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Precision planter monitoring system based on mobile communication network
IET Networks, EarlyView., 2022 Abstract Sowing is an important link in agricultural production and the basis for ensuring high yields and bumper harvests. Agriculture requires precision plows with good performance and stable work. However, the seeding process is in a completely closed state, and the operator relies mainly on experience to judge the operating state and performance of
Bing Li, Jiyun Li
wiley +1 more source
Software-Level Memory Regulation to Reduce Execution Time Variation on Multicore Real-Time Systems
IEEE Access, 2022 Modern real-time embedded systems are equipped with multi-core processors to execute computationally intensive tasks. In multi-core architecture, last-level cache memory is shared by cores.
Sihyeong Park, Jemin Lee, Hyungshin Kim
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Intent Arabic text categorisation based on different machine learning and term frequency
IET Networks, EarlyView., 2022 Abstract The complexity of Internet network configurations has made managing networks a complicated undertaking. Intent‐Based Networking (IBN) is a potential solution to this issue. In contrast to conventional networks, where a concrete description of the settings typically conveys a network administrator's goal kept on each device, an administrator's ...
Mohammad Fadhil Mahdi +1 more
wiley +1 more source
Cache Coherence Protocol Design and Simulation Using IES (Invalid Exclusive read/write Shared) State
مجلة بغداد للعلوم, 2017 To improve the efficiency of a processor in recent multiprocessor systems to deal with data, cache memories are used to access data instead of main memory which reduces the latency of delay time.
Baghdad Science Journal
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Distributed wireless network resource optimisation method based on mobile edge computing
IET Networks, EarlyView., 2022 This paper mainly compares the network ranking leader, consumption amount and network signal reception of the three algorithms. The study found that in terms of network sort captain, there are significant differences between the CPLEX algorithm, the CCST algorithm, and edge computing methods. The CCST algorithm and edge computing have little difference
Jiongting Jiang +4 more
wiley +1 more source
IET Networks, EarlyView., 2023 The topic discussed was the intelligent design of network multimedia using BD and virtual AI technology. First of all, the authors gave a brief overview of its relevant research background, and then comprehensively analysed the advantages and disadvantages of previous scholars' research on network multimedia.
Xin Zhang
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Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs
IEEE Access, 2022 Designs implemented on field-programmable gate arrays (FPGAs) via high-level synthesis (HLS) suffer from off-chip memory latency and bandwidth bottlenecks. FPGAs can access both large but slow off-chip memories (DRAM), and fast but small on-chip memories
Giovanni Brignone +3 more
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Evaluating a number of cache coherency misses based on a statistical model
Труды Института системного программирования РАН, 2018 False cache sharing happens when different parallel execution threads update the variables that reside in the same cache line. We suggest in this paper to evaluate the number of cache misses using code instrumentation and post-mortem trace analysis: the ...
Evgeny Velesevich
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