Results 31 to 40 of about 1,837,572 (294)

An Effective Burst Access Scheme for Lossless Frame Buffer Compression on a Video Decoder

IEEE Access, 2021
For decoding high-resolution image stored in external memory after lossless compression, it is inevitable necessary to allow variable-length data types and this may decreases the efficiency in real time read of arbitrary compressed macro block without ...
Jaeshin Lee, Imjae Hwang, Youngsik Kim, Cheong Ghil Kim, Woo-Chan Park   +4 more
doaj   +1 more source

In-Memory Caching for Enhancing Subgraph Accessibility

Applied Sciences, 2020
Graphs have been utilized in various fields because of the development of social media and mobile devices. Various studies have also been conducted on caching techniques to reduce input and output costs when processing a large amount of graph data.
Kyoungsoo Bok, Seunghun Yoo, Dojin Choi, Jongtae Lim, Jaesoo Yoo   +4 more
doaj   +1 more source

A Heterogeneity-Aware Replacement Policy for the Partitioned Cache on Asymmetric Multi-Core Architectures

Micromachines, 2022
In an asymmetric multi-core architecture, multiple heterogeneous cores share the last-level cache (LLC). Due to the different memory access requirements among heterogeneous cores, the LLC competition is more intense.
Juan Fang, Han Kong, Huijing Yang, Yixiang Xu, Min Cai   +4 more
doaj   +1 more source

BAG : Managing GPU as buffer cache in operating systems [PDF]

, 2014
This paper presents the design, implementation and evaluation of BAG, a system that manages GPU as the buffer cache in operating systems. Unlike previous uses of GPUs, which have focused on the computational capabilities of GPUs, BAG is designed to ...
Tan, Huailiang, Huailiang Tan, Sun, Jianhua, Jianhua Sun, Hao Chen, Kenli Li, Li, Kenli, He, Ligang, Ligang He, Chen, Hao   +9 more
core   +1 more source

An Object-Oriented Library for Shared-Memory Parallel Simulations [PDF]

, 1996
Programming shared-memory multiprocessor systems is becoming increasingly difficult as the gap between memory speed and processor speed increases. At the same time, this class of computer—based on standard microprocessors—is becoming increasingly common ...
Machanick, Philip, Philip Machanick
core   +1 more source

MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches [PDF]

, 2011
SBST (Software Based Self-Testing) is an effective solution for in-system testing of SoCs without any additional hardware requirement. SBST is particularly suited for embedded blocks with limited accessibility, such as cache memories.
Stefano Di Carlo, Rolfo, Daniele, Indaco, Marco, Daniele Rolfo, Gambardella, Giulio, Giulio Gambardella, Paolo Prinetto, Prinetto, Paolo Ernesto, Marco Indaco, Di Carlo, Stefano   +9 more
core   +1 more source

Precision planter monitoring system based on mobile communication network

IET Networks, EarlyView., 2022
Abstract Sowing is an important link in agricultural production and the basis for ensuring high yields and bumper harvests. Agriculture requires precision plows with good performance and stable work. However, the seeding process is in a completely closed state, and the operator relies mainly on experience to judge the operating state and performance of
Bing Li, Jiyun Li
wiley   +1 more source

Proposal New Cache Coherence Protocol to Optimize CPU Time through Simulation Caches [PDF]

Engineering and Technology Journal, 2016
The cache coherence is the most important issue that rapidly affected the performance of a multicore processor as a result of increasing the number of cores on chip multiprocessors and the shared memory program that will be run on these processors ...
Luma Fayeq Jalil, Maha Abdulkareem .H. Al-Rawi, Abeer Diaa Al-Nakshabandi   +2 more
doaj   +1 more source

Intent Arabic text categorisation based on different machine learning and term frequency

IET Networks, EarlyView., 2022
Abstract The complexity of Internet network configurations has made managing networks a complicated undertaking. Intent‐Based Networking (IBN) is a potential solution to this issue. In contrast to conventional networks, where a concrete description of the settings typically conveys a network administrator's goal kept on each device, an administrator's ...
Mohammad Fadhil Mahdi, Mahmoud Shuker Mahmoud   +1 more
wiley   +1 more source

Locality-Based Cache Management and Warp Scheduling for Reducing Cache Contention in GPU

Micromachines, 2021
GPGPUs has gradually become a mainstream acceleration component in high-performance computing. The long latency of memory operations is the bottleneck of GPU performance. In the GPU, multiple threads are divided into one warp for scheduling and execution.
Juan Fang, Zelin Wei, Huijing Yang
doaj   +1 more source