Results 31 to 40 of about 132,994 (259)
Efficient Simulation Of Cache Memories [PDF]
1989 Winter Simulation Conference Proceedings, 1989 Cache memories are used in computer systems to reduce average memory access times. Existing techniques for predicting cache performance are often unsatisfactory in terms of cost or performance. This paper presents a method for efficiently simulating the effects of a cache on the execution time of a program.
S. Dwarkadas, J. R. Jump, J. B. Sinclair
openaire +1 more source
IET Networks, EarlyView., 2023 The topic discussed was the intelligent design of network multimedia using BD and virtual AI technology. First of all, the authors gave a brief overview of its relevant research background, and then comprehensively analysed the advantages and disadvantages of previous scholars' research on network multimedia.
Xin Zhang
wiley +1 more source
Cache Coherence Protocol Design and Simulation Using IES (Invalid Exclusive read/write Shared) State
مجلة بغداد للعلوم, 2017 To improve the efficiency of a processor in recent multiprocessor systems to deal with data, cache memories are used to access data instead of main memory which reduces the latency of delay time.
Baghdad Science Journal
doaj +1 more source
Software-Level Memory Regulation to Reduce Execution Time Variation on Multicore Real-Time Systems
IEEE Access, 2022 Modern real-time embedded systems are equipped with multi-core processors to execute computationally intensive tasks. In multi-core architecture, last-level cache memory is shared by cores.
Sihyeong Park, Jemin Lee, Hyungshin Kim
doaj +1 more source
Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs
IEEE Access, 2022 Designs implemented on field-programmable gate arrays (FPGAs) via high-level synthesis (HLS) suffer from off-chip memory latency and bandwidth bottlenecks. FPGAs can access both large but slow off-chip memories (DRAM), and fast but small on-chip memories
Giovanni Brignone +3 more
doaj +1 more source
, 2005 We explore the use of compiler optimizations, which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying hardware resources regardless of the specific details of the processor/architecture ...
Larriba Pey, Josep +2 more
core +2 more sources
Caching in Web memory hierarchies [PDF]
Proceedings of the 2004 ACM symposium on Applied computing, 2004 Web cache replacement algorithms have received a lot of attention during the past years. Though none of the proposed algorithms deals efficiently with all the particularities of the Web environment, namely, relatively weak temporal locality (due to filtering effects of caching hierarchies), heterogeneity in size and origin of request streams.
Dimitrios Katsaros 0001 +1 more
openaire +1 more source
Three-dimensional memory vectorization for high bandwidth media memory systems [PDF]
, 2002 Vector processors have good performance, cost and adaptability when targeting multimedia applications. However, for a significant number of media programs, conventional memory configurations fail to deliver enough memory references per cycle to feed the ...
Corbal San Adrián, Jesús +2 more
core +1 more source
Evaluating a number of cache coherency misses based on a statistical model
Труды Института системного программирования РАН, 2018 False cache sharing happens when different parallel execution threads update the variables that reside in the same cache line. We suggest in this paper to evaluate the number of cache misses using code instrumentation and post-mortem trace analysis: the ...
Evgeny Velesevich
doaj +1 more source
Defending cache memory against cold-boot attacks boosted by power or EM radiation analysis [PDF]
, 2017 Some algorithms running with compromised data select cache memory as a type of secure memory where data is confined and not transferred to main memory. However, cold-boot attacks that target cache memories exploit the data remanence. Thus, a sudden power
Manich Bou, Salvador, Neagu, Madalin
core +2 more sources