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Design and Implementation of SIMD Unaligned Memory Access Structure [PDF]
Jisuanji gongcheng, 2016 Single Instruction Multiple Data(SIMD) is an effective approach to realize data level parallelism,but accessing unaligned data seriously affects vectorization of the program and causes processor performance degradation.In order to reduce the latency of ...
YU Chenglong,WANG Yongwen
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Optimization of data allocation in hierarchical memory for blocked shortest paths algorithms
Системный анализ и прикладная информатика, 2021 This paper is devoted to the reduction of data transfer between the main memory and direct mapped cache for blocked shortest paths algorithms (BSPA), which represent data by a D[M×M] matrix of blocks.
A. A. Prihozhy
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InformationThis paper presents a register-transfer-level (RTL) fault injection study of the LEON3 processor’s internal memory subsystem under single-event upsets (SEUs). The analysis targets four key components: the instruction cache (I-cache), data cache (D-cache),
Afef Kchaou, Sehmi Saad, Hatem Garrab
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Data in Brief, 2015 Cache blocking is a technique widely used in scientific computing to minimize the exchange of information with main memory by reusing the data kept in cache memory.
Jose-Ignacio Agulleiro +1 more
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Impact of Memory Hierarchy on Memory Encryption Performance
IEEE AccessMemory encryption with authentication protects critical applications from attackers with physical access. Memory encryption introduces memory access latency overhead due to the cryptographic computations and metadata accesses in DRAM.
Viktor V. Prutyanov +4 more
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Memory Caching: RNNs with Growing Memory
CoRRTransformers have been established as the de-facto backbones for most recent advances in sequence modeling, mainly due to their growing memory capacity that scales with the context length. While plausible for retrieval tasks, it causes quadratic complexity and so has motivated recent studies to explore viable subquadratic recurrent alternatives ...
Ali Behrouz +5 more
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A Sampling Algorithm for Software Prefetching Using Memory Access Traces [PDF]
Jisuanji gongchengSoftware prefetching, an important technology for improving data access performance, has received widespread attention and has been used in several applications.
LIU Daxing, GU Naijie, HUANG Zhangjin, SU Junjie, QI Dongsheng
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Defending Against Flush+Reload Attack With DRAM Cache by Bypassing Shared SRAM Cache
IEEE Access, 2020 Cache side-channel attack is one of the critical security threats to modern computing systems. As a representative cache side-channel attack, Flush+Reload attack allows an attacker to steal confidential information (e.g., private encryption key) by ...
Minwoo Jang +3 more
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A Simple Cache Emulator for Evaluating Cache Behavior for SMP Systems
Acta Polytechnica, 2006 Every modern CPU uses a complex memory hierarchy, which consists of multiple cache memory levels. It is very difficult to predict the behavior of this hierarchy for a given program (for details see [1, 2]).
I. Šimeček
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Future InternetInformation-Centric Networking (ICN) typically utilizes DRAM (Dynamic Random Access Memory) to build in-network cache components due to its high data transfer rate and low latency. However, DRAM faces significant limitations in terms of cost and capacity,
Yichao Chao, Rui Han
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