Системный анализ и прикладная информатика, 2019 Caches are intermediate level between fast CPU and slow main memory. It aims to store copies of frequently used data and to reduce the access time to the main memory.
A. A. Prihozhy
doaj +1 more source
LRC: Dependency-Aware Cache Management for Data Analytics Clusters
, 2017 Memory caches are being aggressively used in today's data-parallel systems such as Spark, Tez, and Piccolo. However, prevalent systems employ rather simple cache management policies--notably the Least Recently Used (LRU) policy--that are oblivious to the
Letaief, Khaled Ben +3 more
core +2 more sources
Measurement-based modeling of the cache replacement policy [PDF]
2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), 2013 Modern microarchitectures employ memory hierarchies involving one or more levels of cache memory to hide the large latency gap between the processor and main memory. Cycle-accurate simulators, self-optimizing software systems, and platform-aware compilers need accurate models of the memory hierarchy to produce useful results.
Andreas Abel 0002, Jan Reineke 0001
openaire +1 more source
Exploring the Latency Sensitivity of Cache Replacement Policies
IEEE Computer Architecture Letters, 2023 With DRAM latencies increasing relative to CPU speeds, the performance of caches has become more important. This has led to increasingly sophisticated replacement policies that require complex calculations to update their replacement metadata, which often require multiple cycles.
Ahmed Nematallah +2 more
openaire +2 more sources
Energy-Efficient Shared Cache Using Way Prediction Based on Way Access Dominance Detection
IEEE Access, 2021 To meet the performance demands of chip multiprocessors, chip designers have increased the capacity and hierarchy of cache memories. Accordingly, a shared lower-level cache reduces conflict misses by adopting a multi-way set-associative structure with ...
Yun-Seok Oh, Eui-Young Chung
doaj +1 more source
Software-Based Self-Test of Set-Associative Cache Memories [PDF]
, 2011 Embedded microprocessor cache memories suffer from limited observability and controllability creating problems during in-system tests. This paper presents a procedure to transform traditional march tests into software-based self-test programs for set ...
Di Carlo, Stefano +2 more
core +1 more source
Using Grouped Linear Prediction and Accelerated Reinforcement Learning for Online Content Caching
, 2018 Proactive caching is an effective way to alleviate peak-hour traffic congestion by prefetching popular contents at the wireless network edge. To maximize the caching efficiency requires the knowledge of content popularity profile, which however is often ...
Tao, Meixia, Zhang, Naifu, Zheng, Kaibin
core +1 more source
Hardware-Based Implementation of Algorithms for Data Replacement in Cache Memory of Processor Cores
ComputersReplacement policies have an important role in the functioning of the cache memory of processor cores. The implementation of a successful policy allows us to increase the performance of the processor core and the computer system as a whole.
Larysa Titarenko +4 more
doaj +1 more source
An Efficient Cache Strategy in Information Centric Networking Vehicle-to-Vehicle Scenario
IEEE Access, 2017 Information centric networking (ICN) has been recently proposed as a prominent solution for content delivery in vehicular ad hoc networks. By caching the data packets in vehicular unused storage space, vehicles can obtain the replicate of contents from ...
Weicheng Zhao +4 more
doaj +1 more source
Adapting ACME to the database caching environment : a thesis presented in partial fulfilment of the requirements for the degree of Master of Science in Information Systems at Massey University [PDF]
, 2003 The field of database cache replacement has seen a great many replacement policies presented in the past few years. As the challenge to find the optimal replacement policy continues, new methods and techniques of determining cache victims have been ...
Riaz-ud-Din, Faizal
core