Results 201 to 210 of about 13,514 (257)

A quadrature RC-oscillator with capacitive coupling

The Integration VLSI Journal, 2016
In this paper the capacitive coupling in quadrature RC-oscillators is investigated. The capacitive coupling has the advantages of being noiseless with a small area penalty and without increasing the power dissipation. The results show that a phase error below 1?
Luis Bica Oliveira, Igor Filanovsky, João Casaleiro   +2 more
exaly   +3 more sources

Semipermanent Storage by Capacitive Coupling

IEEE Transactions on Electronic Computers, 1961
The need arises for reliable, economical high-speed, semipermanent stores for electronic-telephone switching systems, as well as for modern digital computers. A semipermanent or fixed store is one in which the stored information may not be changed by the machine that is able to consult it.
Donald H. MacPherson, Robert K. York
openaire   +1 more source

XREF coupling: capacitive coupling error checker

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers, 2002
Capacitive coupling among critical nodes in a CMOS VLSI circuit can cause disastrous effects on the logical operation of the circuit. At present, the only simulation method that can accurately detect global capacitive coupling errors is the classical circuit simulation, which, due to its limited capacity, is not practical to apply to the entire design.
William J. Grundmann, Yao-Tsung Yen
openaire   +1 more source

Capacitive coupling clamp

2008 16th International Conference on Software, Telecommunications and Computer Networks, 2008
This paper reports on a great area of electromagnetic compatibility. Special attention is given to measurement of electromagnetic interference established via the cable. A capacitive coupling clamp that conforms to requirements of ISO 64000-4-4 is built for measuring the resistance of three different cables (a twisted pair, RG – 58A/U and RG ...
Radman, Slavko, Bačić, Iva, Malarić, Krešimir   +2 more
openaire   +2 more sources

An on-chip coupling capacitance measurement technique

VLSI Design 2001. Fourteenth International Conference on VLSI Design, 2002
We describe a technique for the accurate measurement of on-chip coupling capacitance using a Charge Based Coupling Capacitance Measurement (CBCCM) Technique. Detailed circuit simulations show that this method can measure sub-femtofarad coupling capacitance values, and can be used to isolate and measure components of device capacitance as well.
NAIR, PA, GUPTA, A, DESAI, MP
openaire   +2 more sources

Capacitive Coupled Communication

2010
Capacitive coupled communication is a wireless chip to chip communication technology that uses capacitive coupling to transfer signals from a chip to neighboring chips. Its high-bandwidth, low-power, and low-latency chip-to-chip I/O capabilities enable the construction of high-performance and economical multi-chip modules (MCMs).
David Hopkins, Alex Chow, Frankie Liu, Dinesh D. Patil, Hans Eberle   +4 more
openaire   +1 more source

Synchronization Phenomena in Microgrids With Capacitive Coupling

IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2015
Multiple converters connected to a microgrid must have the same clock frequency, else interaction among the frequencies may cause beating noise. But the frequency equalization is difficult to achieve in practice. We show that the nonlinearity present in all power electronic systems offers an interesting possibility: the clocks may synchronize ...
Kuntal Mandal, Soumitro Banerjee
openaire   +1 more source

Accurate Decoupling of Capacitively Coupled Buses

2005 IEEE International Symposium on Circuits and Systems, 2005
This paper proposes a fast and accurate algorithm to decouple the lines of capacitively coupled buses. Simulation results show that the proposed algorithm accurately estimates the equivalent capacitances and delay of the coupled buses with an average error of 3.0% and a maximum error of 4.5%.
Maged Ghoneima, Yehea I. Ismail
openaire   +1 more source

A Capacitance-Coupled Bit Line Cell

IEEE Journal of Solid-State Circuits, 1985
A 38-µm2dynamic random-access memory (dRAM) cell with a capacitance-coupled bit line (CCB) approach is described. This cell enables a storage capacitor area 2-2.5 times larger than double polysilicon-type cells, or half the cell area with the same design rules.
M. Taguchi, S. Ando, S. Hijiya, T. Nakamura, S. Enomoto, T. Yabu   +5 more
openaire   +1 more source