Results 1 to 10 of about 54,322 (165)
In this study, we present a novel type of package, freeform-designed chip scale package (FDCSP), which has ultra-high light extraction efficiency and bat-wing light field.
Che-Hsuan Huang +9 more
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Wafer-level chip-scale packages have been extensively adopted in the electronic packaging industry owing to their ability to enhance device performance.
Tae Kyun Kim +3 more
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Thermal and magnetic field analysis of temperature control module for VCSEL chips
VCSEL chips with wavelengths in the range of 700 nm–800 nm, the same as the transition spectral lines of alkali atoms, can be used as light sources for novel miniaturized quantum sensors.
Dezhao Li +5 more
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Wafer level chip scale package (WLCSP) is true chip scale package with low cost by eliminating package substrate. The direct chip-to-board attach through solder joints provides low interconnect inductance and resistance, as well as improved thermal ...
Zhuo-Jie Wu +2 more
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A Review of Design and Integration Technologies for D-Band Antennas
This article reviews the current state-of-the-art of millimeter-wave (mm-wave) antennas for communication and sensing applications in the D-band between 110 and 170 GHz.
Martijn de Kok +2 more
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Development of Reliable, High Performance WLCSP for BSI CMOS Image Sensor for Automotive Application
To meet the urgent market demand for small package size and high reliability performance for automotive CMOS image sensor (CIS) application, wafer level chip scale packaging (WLCSP) technology using through silicon vias (TSV) needs to be developed to ...
Tianshen Zhou +4 more
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ChIP-BIT2: a software tool to detect weak binding events using a Bayesian integration approach
Background ChIP-seq combines chromatin immunoprecipitation assays with sequencing and identifies genome-wide binding sites for DNA binding proteins. While many binding sites have strong ChIP-seq ‘peak’ observations and are well captured, there are still ...
Xi Chen +5 more
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Design and fabrication of cryogenic multiplexing control chip
This paper presents a design and fabrication process of a cryogenic multiplexing control chip (MCC) for superconducting quantum computers. The working temperature of MCC can be 10 ∼ 30 mK, because it could be integrated with quantum processor in the same
Rutian Huang +12 more
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Challenges and recent prospectives of 3D heterogeneous integration
With the continuous reduction of chip feature size, the continuation of Moore's Law becomes increasingly difficult and heterogeneous integration has become one of the important orientations of electronic technology.
Shuye Zhang +6 more
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This article combines the sequential artificial neural network (NN) machine learning with finite element (FE) modeling to assess the solder joint thermal cycling performance. A glass wafer-level chip-scale package (G-WLCSP) is used for this study.
Cadmus C. A. Yuan, Chang-Chi Lee
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