Results 241 to 250 of about 34,539 (304)

Clock neurons gate memory extinction in Drosophila

Current Biology, 2021
Memory forms when a previously neutral stimulus (CS+) becomes competent to predict a biologically potent stimulus (US). However, if the CS+ is repeatedly presented without the US after the memory formation, this memory will be suppressed by newly formed extinction memory.1,2 The striking feature of extinction learning is that it requires repeated ...
Yunchuan Zhang, Yinzhong Zhou, Xuchen Zhang, Lingling Wang, Yi Zhong   +4 more
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Complex clock gating with integrated clock gating logic cell

2007 International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2007
Clock gating is an effective technique for minimizing dynamic power in sequential circuits. Applying clock-gating at gate-level not only saves time compared to implementing clock-gating in the RTL code but also saves power and can easily be automated in the synthesis process.
Rani Bhutada, Yiannos Manoli
openaire   +1 more source

Clock tree construction using gated clock cloning

2012 4th Asia Symposium on Quality Electronic Design (ASQED), 2012
Clock gating is one of the important techniques to achieve low power and small area in high-performance synchronous circuit design. In this paper, we propose a three-phase clock gating optimization methodology by using clustering and merging algorithm to construct a gated clock tree with minimal number of clock gating cells and buffers.
null Wun-Han Chen, null Hsin-Hung Chang, null Jui-Hung Hung, null Tsai-Ming Hsieh   +3 more
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Clock Gate Test Points

2010 IEEE International Test Conference, 2010
Clock gating is widely used in modern integrated circuits as a means of reducing dynamic power consumption. In this paper we present a comprehensive analysis of the impact of clock gating during test. We then propose a new type of test point called Clock Gate Test Points.
Narendra Devta-Prasanna, Arun Gunda
openaire   +1 more source

Gate planning during placement for gated clock network

2008 IEEE International Conference on Computer Design, 2008
Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous approaches still have a significant weakness. That is, they usually construct a gated clock tree after cell placement, i.e., cell placement is performed without considering clock gating ...
null Weixiang Shen, null Yici Cai, null Xianlong Hong, null Jiang Hu   +3 more
openaire   +1 more source

Clock-Gating in FPGAs: A Novel and Comparative Evaluation

9th EUROMICRO Conference on Digital System Design (DSD'06), 2006
Clock-gating has been employed in low-power FPGA designs based on an emulated and compromised method. So far in literature the actual efficiency of savings in power consumption is not thoroughly studied for this method. In this paper we evaluated the clock-gating technique in FPGAs, based on a novel and comparative process.
Roivainen, Jussi, Mämmelä, Aarne, Zhang, Yan   +3 more
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Resurrecting infeasible clock-gating functions

Proceedings of the 46th Annual Design Automation Conference, 2009
In this paper we consider the problem of exploiting infeasible clock gating functions. Analysis of industrial designs reveals a large margin of potential for power saving based on clock gating functions that initially appear to be useless due to timing violation or excessive power consumption.
Eli Arbel, Cindy Eisner, Oleg Rokhlenko
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Clock Gating Techniques: An Overview

2018 Conference on Emerging Devices and Smart Systems (ICEDSS), 2018
Clock gating is one of the most popular techniques used in many synchronous circuits for reducing dynamic power dissipation and it is helpful for decreasing the ability of power wasted by digital circuits. The major power consuming in electronics product is the systems clock signal and it is responsible for transition state of the components and this ...
Tamil Chindhu S., N. Shanmugasundaram
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Clock-gated harmonic rejection mixers

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
In this paper, harmonic-rejection mixers (HRM) in which incoming radio frequency (RF) signal is multiplied by square-wave local-oscillator (LO) output, are described. Starting with the generalization of the conventional HRM concept, a technique to reject higher order harmonics, above the third and fifth, is presented.
Aslam A. Rafi, T. R. Viswanathan
openaire   +1 more source