Results 251 to 260 of about 34,539 (304)

Regional clock gate splitting algorithm for clock tree synthesis

2010 IEEE International Conference on Semiconductor Electronics (ICSE2010), 2010
In this paper, the new clock distribution design flow and algorithm of clock gate splitting to improve the clock gate's enable signal timing violations had been presented. The clock gate components in a clock tree are exposed to setup timing violations due to the nature that the clock gates skew is normally big as they are located at the beginning of ...
Siong Kiong Teng, Norhayati Soin
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Clock Gating Integration Using 18T-TSPC Clocked Flip Flop

2019 2nd International Conference on Intelligent Computing, Instrumentation and Control Technologies (ICICICT), 2019
Flip-flops are a standout among the most significant and fundamental block of any advanced circuits. The power being on the main consideration in planning of the advanced circuits must be enhanced to improve the exhibition of the circuit. There are many low power techniques accessible to diminish the power dispersal. The thought here is to join the low
Akshay S Mangawati, Namita Palecha
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Power Optimization Using Clock Gating and Power Gating

2016
The scaling of CMOS technology has continued due to ever increasing demand of greater performance with low power consumption. This demand has grown further by the portable and battery operated devices market. To meet the challenge of greater energy efficiency and performance, a number of power optimization techniques at processor and system components ...
Arsalan Shahid, Saad Arif, Muhammad Yasir Qadri, Saba Munawar   +3 more
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Clock gating and clock enable for FPGA power reduction

2012 VIII Southern Conference on Programmable Logic, 2012
This paper presents experimental measurements of power consumption using different techniques to turn off part of a system and switch between active and standby modes. The main ideas analyzed are: clock gating, clock enable, and blocking inputs. The laboratory work is described, including the measurement setups and the benchmark circuits.
J. P. Oliver, J. Curto, D. Bouvier, M. Ramos, E. Boemo   +4 more
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Type-matching clock tree for zero skew clock gating

Proceedings of the 45th annual Design Automation Conference, 2008
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR gates, and buffer gates. If the logic gates at the same level are in different types, which have different timing behaviors, the control of clock skew becomes difficult.
Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu   +5 more
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Low power clock gates optimization for clock tree distribution

2010 11th International Symposium on Quality Electronic Design (ISQED), 2010
Clock gating technique had become one of the major dynamic power saving approaches in today low power digital circuit design. In this paper, we present a new physical clock gates optimization technique using splitting and merging algorithm that works on both single level and multiple levels clock gating design.
Siong Kiong Teng, Norhayati Soin
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Clock gating assertion check: An approach towards achieving faster verification closure on clock gating functionality

2015 6th Asia Symposium on Quality Electronic Design (ASQED), 2015
Clock gating is a power reduction technique widely used in Register Transfer Level (RTL) stage of a chip design. The addition of clock gating logics has increased the complexity of a design and therefore requires considerable amount of verification effort.
Wang Jian Zhong, Norlaili Mohd Noh, Bakhtiar Affendi Rosdi   +2 more
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A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012
This paper presents a clock polarity assignment flow which permits post-silicon reconfigurability. The proposed method inserts xor gates at one level of the clock tree to facilitate the polarity assignment. The polarity of the xor gates can be reconfigured for different modes of clock gating (sleep mode, busy mode, etc.) such that a mode-specific ...
Jianchao Lu, Ying Teng, Baris Taskin
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Clock Gating and Negative Edge Triggering for Energy Recovery Clock

2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2007
Energy recovery clocking has been demonstrated as an effective method for reducing the clock power. In this method the conventional square wave clock signal is replaced by a sinusoidal clock generated by a resonant circuit. Such a modification in clock signal prevents application of existing clock gating solutions.
Vishwanadh Tirumalashetty, Hamid Mahmoodi   +1 more
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The application of automatic gating clock in SoC clock network

2009 9th International Conference on Electronic Measurement & Instruments, 2009
This paper makes research on automatic gating clock technology in SoC clock network. Based on SoC1000 CPU core, analyze the characters of its inner time logic and combine ASIC physical design flow and method based on standard unit. This paper puts forward a clock network scheme based on precise credible time analysis. This method can greatly reduce SoC
Tao Li, Yilei Wang, Shixiang Jia
openaire   +1 more source