Results 261 to 270 of about 34,539 (304)

Clock Gating-Assisted Malware (CGAM): Leveraging Clock Gating On ARM Cortex M For Attacking Subsystems Availability

2021 9th International Symposium on Digital Forensics and Security (ISDFS), 2021
Due to the ever-increasing demand for developing Internet of Things (IoT) technologies that support low power consumption and high-performance mobile computing, several power optimization techniques have been implemented and deployed at the processors level, especially the ARM Cortex-M family chipsets. Such techniques include clock gating, power gating,
Amar A. Rasheed, Hacer Varol, Mohamed Baza   +2 more
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A verification technique for gated clock

Proceedings of the 30th international on Design automation conference - DAC '93, 1993
We present a new model for circuits which have memory elements using conditional clocking. This is termed as the "gated" clock problem. Conventionally most of the recent efforts in timing analysis focus on memory elements controlled by clock signals only.
Masamichi Kawarabayashi, Narendra Shenoy, Alberto Sangiovanni-Vincentelli   +2 more
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Power-Clock Gating

2012
A very efficient and easy to implement method to cut down energy losses in idle times is proposed, the so-called power-clock gating. The basic idea is to use a switch to disconnect the power-clock from the adiabatic circuit when no operations are performed in the system. The theory to power-clock gating is presented and figures are derived to allow for
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Clock gating optimization with delay-matching

2011 Design, Automation & Test in Europe, 2011
Clock gating is an effective method of reducing power dissipation of a high-performance circuit. However, deployment of gated cells increases the difficulty of optimizing a clock tree. In this paper, we propose a delay-matching approach to addressing this problem. Delay-matching uses gated cells whose timing characteristics are similar to that of their
null Shih-Jung Hsu, null Rung-Bin Lin
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Test power optimization using clock gating

2017 International Conference on Intelligent Computing, Instrumentation and Control Technologies (ICICICT), 2017
The major factor in VLSI design process is low power testing. Modern ICs consists of more transistors in a single chip due to which testing becomes challenging since it consumes more power than functionality of the circuits. System clock signal in electronics product consumes the important part of dynamic power, among them 70% is spent by clock buffers.
K Madhushree, Niju Rajan
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Efficient Automated Clock Gating Using CoDeL

2006
We present a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. Our language, called CoDeL, allows hardware description at the algorithm level, and thus dramatically reduces design time. We have extended CoDeL to automatically insert clock gating at the behavioral level to reduce dynamic ...
Nainesh Agarwal, Nikitas J. Dimopoulos
openaire   +1 more source

Formal representation of gated clock designs

Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541), 2002
The action systems formal framework has recently been applied to the area of asynchronous and synchronous VLSI design. In this paper, we present aspects of formal gated clock design. This proves useful when targeting mixed-architecture designs: devices composed of subsystems that operate in an asynchronous manner with respect to each other, even though
T. Seceleanu, J. Plosila
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Clock-controlled neuron-MOS logic gates

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1998
A new clock-controlled circuit scheme has been introduced in the basic architecture of neuron-MOS (neuMOS or /spl nu/MOS) logic gates. In this scheme, the charge on a neuMOS floating gate is periodically refreshed by a clock-controlled switch. A special refreshing scheme in which fluctuations in device parameters are automatically canceled has been ...
K. Kotani, T. Shibata, M. Imai, T. Ohmi
openaire   +1 more source

Low power compression utilizing clock-gating

2011 IEEE International Test Conference, 2011
Growing test data volume and excessive test power consumption in scan testing are both serious concerns for the semiconductor industry. This paper presents a method to simultaneously reduce test data volume and test power utilizing clock gating. This is achieved through not clocking a high proportion of scan chains during both scan shift and test ...
Janusz Rajski, Elham K. Moghaddam, Sudhakar M. Reddy   +2 more
openaire   +1 more source

Low-power flip-flops with reliable clock gating

Microelectronics Journal, 2001
Abstract The paper presents two gated flip-flops aimed at low-power applications. The proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. The presented circuits overcome the clock duty-cycle limitation of previously reported gated flip-flops.
STROLLO, ANTONIO GIUSEPPE MARIA, NAPOLI, ETTORE, DE CARO, Davide   +2 more
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