Results 271 to 280 of about 34,539 (304)

Clock Feedthrough in CMOS Analog Transmission Gate Switches

Analog Integrated Circuits and Signal Processing, 2003
An analysis of clock feedthrough in CMOS analog transmission gate (TG) switches is presented in this paper. The mechanism for clock feedthrough and a related model of a transmission gate switch are established in the current-voltage domain. A region map is developed for the TG switch during the period when both devices are turned off. The region map is
null Weize Xu, E.G. Friedman
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Improved clock-gating through transparent pipelining

Proceedings of the 2004 international symposium on Low power electronics and design, 2004
This paper re-examines the well established clocking principles of pipelines. It is observed that clock gating techniques that have long been assumed optimal in reality produce a significant amount of redundant clock pulses. The paper presents a new theory for optimal clocking of synchronous pipelines, presents practical implementations and evaluates ...
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100 Mc/s gated clock oscillator

Nuclear Instruments and Methods, 1967
Abstract A simple gated clock oscillator is analyzed, where gating pulse rise and fall times are comparable to the period of oscillations. Resonator response to ramp forcing function assuming a linear damping device is found and curves for calculating the amplitude and initial phase angle of the oscillation are shown.
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Test Strategies for Gated Clock Designs

2009
One of the ways often used to design for low-power consumption during functional operation in CMOS devices is to gate off clocks to areas of logic not needed for the current state of operation. By gating off clocks to state elements that are known to not need updating, the dynamic switching current can be reduced compared with allowing state elements ...
Brion Keller, Krishna Chakravadhanula
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Clock Domain Crossing Aware Sequential Clock Gating

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2015
Jianfeng Liu, Mi-Suk Hong, Kyungtae Do, Jung Yun Choi, Jaehong Park, Mohit Kumar, Manish Kumar, Nikhil Tripathi, Abhishek Ranjan   +8 more
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Reducing Clock Power by Using the Clock Gating Technique

2023
Garad Ashutosh, Musale Jivan, Garad Shraddha, Pawar Rahul   +3 more
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Integrative oncology: Addressing the global challenges of cancer prevention and treatment

Ca-A Cancer Journal for Clinicians, 2022
Jun J Mao,, Msce, Lorenzo Cohen, Karen M Mustian   +2 more
exaly  

Low Power Sorters Using Clock Gating

2021 IEEE International Symposium on Smart Electronic Systems (iSES), 2021
Preethi Preethi, K.G Mohan, K Sudeendra Kumar, K. K. Mahapatra   +3 more
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Using gated clock in ASIC design

2022 3rd International Conference on Electronics, Communications and Information Technology (CECIT), 2022
Chen Jingguo, Yan Yongming
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Pulser gating: A clock gating of pulsed-latch circuits

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 2011
Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin   +3 more
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