Results 191 to 200 of about 407,225 (353)
Photoinduced patterning of inorganic materials promises advanced functionality, but often suffers from granular structures. Here, UV‐triggered dephosphorylation is used to guide the precipitation of barium phosphate with spatial control and structural continuity.
Patricia Besirske +5 more
wiley +1 more source
Spatial uniformity and temporal stability of pixel-to-pixel variation in mini-SiTian CMOS detector. [PDF]
Hu G +16 more
europepmc +1 more source
Opportunities for Multiscale Pattern Modulation with Temporally Arrested Breath Figures
This works presents the temporally arrested breath figure methodology and its opportunities for pattern modulation. Through thermodynamic and photochemical phase change handles, this method uses drop‐wise condensation as a dynamic template for fast, accessible and scalable micropatterning.
Francis J. Dent +5 more
wiley +1 more source
A full-featured 2D flash chip enabled by system integration. [PDF]
Liu C +13 more
europepmc +1 more source
Spin‐coated films of the conjugated polymer F8T2 (poly (9,9‐dioctylfluorene‐alt‐bithiophene)) generate superoxide at the film‐medium interface, enabling precise delivery of reactive oxygen species (ROS) as visible‐light “ROS patches.” Coated surfaces drive rapid, localised cytotoxicity in MCF7 cancer monolayers under white light, providing a reagent ...
Joe Kaye +8 more
wiley +1 more source
Structures and Chemical Bonding of B<sub>5</sub>O<sub>7</sub> <sup>+/0/-</sup> with a Hexagonal B<sub>3</sub>O<sub>3</sub> Ring†. [PDF]
Gao SJ, Hu C, Li F, Wang L.
europepmc +1 more source
Printed Interconnects for Heterogeneous Systems Integration on Flexible Substrates
Key components (sensors, energy devices, communication devices, computing chips, and interconnects) of flexible hybrid electronic (FHE) system connected via conductive printed metal tracks. The figure in the insets shows out‐of‐plane printed interconnects providing opportunities for lithography‐free formation of VIAs, in‐plane access of UTCs pads, and ...
Abhishek Singh Dahiya +3 more
wiley +1 more source
Low power and high-speed quadrate node upset tolerant latch design using CNTFET. [PDF]
Asiya S, S SK.
europepmc +1 more source

