Results 191 to 200 of about 385,801 (356)
<title>CMOS processor element for a fault-tolerant SVD array</title> [PDF]
Kishore Kota, Joseph R. Cavallaro
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This work presents a systematic review of atmospheric turbulence fundamentals, including theoretical formulations and adaptive optics‐based mitigation strategies. This includes an in‐depth examination of the devices, theories, and methodologies associated with traditional correction approaches.
Qinghui Liu+5 more
wiley +1 more source
Relationship between IBICC imaging and SEU in CMOS ICs [PDF]
F.W. Sexton+6 more
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The fabrication of 940 micro‐light‐emitting diodes on both 300 mm Si and Ge/Si wafers has been demonstrated using direct metal–organic chemical vapor deposition epitaxy. These promising results show the potential for monolithic integration of III‐As onto complementary metal‐oxide‐semiconductor (CMOS)‐compatible silicon platforms. This achievement opens
Hadi Hijazi+12 more
wiley +1 more source
An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits [PDF]
Farid N. Najm, I.N. Hajj, Ping Yang
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Optical wireless communications (OWCs) provide a promising alternative to spectrum‐congested microwave wireless communications. Recently, the use of metasurfaces with sub‐wavelength features for dynamic beam steering, beam manipulation, and spatial or optical‐angular‐momentum mode generation, conversion, and multiplexing in OWCs is proposed and ...
Ke Wang+7 more
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A CMOS peak detect sample and hold circuit [PDF]
M.W. Kruiskamp, D.M.W. Leenaerts
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High‐Throughput Single‐Nanowire Optoelectronic Characterization Using Microfluidic Technology
An ultrathin microfluidic platform enables high‐throughput, in‐line single particle characterization of semiconductor nanowires. Using correlative spectroscopy and imaging, analysis at 240 nanowires per minute, uncovering previously hidden details about intra‐wire disorder and inter‐wire inhomogeneity, is achieved.
Tharaka MDS Weeraddana+5 more
wiley +1 more source
Effect of post-metallization anneal on monolithic co-integration of Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub>-based FeFET and CMOS. [PDF]
An J+7 more
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Bridge fault simulation strategies for CMOS integrated circuits [PDF]
B. Chess, T. Larrabee
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