Results 211 to 220 of about 47,494 (264)
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A CMOS fuse for safe release of CMOS-MEMS devices
2017 IEEE SENSORS, 2017This paper reports a safe release mechanism for MEMS devices fabricated using plasma etching based dry processes. The proposed smart fuse is particularly designed for CMOS-MEMS devices where inherent CMOS thin films are used as structural materials. Properly designed polysilicon heater sandwiched between CMOS layers is the critical element of the fuse.
Peng Qu, Hongwei Qu
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IEEE Journal of Solid-State Circuits, 2005
A direct-conversion ultra-wideband (UWB) transceiver for Mode 1 OFDM applications employs three resonant networks and three phase-locked loops. Using a common-gate input stage, the receiver allows direct sharing of the antenna with the transmitter. Designed in 0.13-/spl mu/m CMOS technology, the transceiver provides a total gain of 69-73 dB and a noise
Behzad Razavi +8 more
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A direct-conversion ultra-wideband (UWB) transceiver for Mode 1 OFDM applications employs three resonant networks and three phase-locked loops. Using a common-gate input stage, the receiver allows direct sharing of the antenna with the transmitter. Designed in 0.13-/spl mu/m CMOS technology, the transceiver provides a total gain of 69-73 dB and a noise
Behzad Razavi +8 more
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Implementation of CMOS oscillator for CMOS SAW resonator
2016 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2016This work presents a design and measurement of pierce oscillator circuit for microelectromechanical system (MEMS) SAW resonator. The pierce oscillator circuit was fabricated using MIMOS 0.35um CMOS technology process. The pierce oscillator circuit provides gain to offset the losses of the resonator.
Jamilah Karim, Anis Nurashikin Nordin S.
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Generalised CMOS---a technology independent CMOS IC design style
Proceedings of the 22nd ACM/IEEE conference on Design automation - DAC '85, 1985A CMOS IC design methodology is presented which allows a single design representation, captured at the symbolic level, to be implemented in different classes of CMOS fabrication technologies such as N-well, P-well, twin-well, and SOI. Extensive use is made of CAD tools to achieve automatic conversion from the technology-independent representation into ...
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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044), 2002
The VLSI industry is accelerating towards the end of scaling (bulk) CMOS. Near its scaling limit, a CMOS transistor could have a channel length of about 25 nm, a switching speed about three times as fast as a device of 100-nm channel length, and an f/sub T/ of about 250 GHz.
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The VLSI industry is accelerating towards the end of scaling (bulk) CMOS. Near its scaling limit, a CMOS transistor could have a channel length of about 25 nm, a switching speed about three times as fast as a device of 100-nm channel length, and an f/sub T/ of about 250 GHz.
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Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 2005
B. Courtoi, Michael R. B. Forshaw
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B. Courtoi, Michael R. B. Forshaw
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IBM Journal of Research and Development, 2000
The performance of integrated circuits has been improving exponentially for more than thirty years. During the next decade, the industry must overcome several technological challenges to sustain this remarkable pace of improvement. Challenges in lithography, transistor scaling, interconnections, circuit families, computer memory, and circuit design are
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The performance of integrated circuits has been improving exponentially for more than thirty years. During the next decade, the industry must overcome several technological challenges to sustain this remarkable pace of improvement. Challenges in lithography, transistor scaling, interconnections, circuit families, computer memory, and circuit design are
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International Journal of Circuit Theory and Applications, 1995
PALMISANO, Giuseppe, PALUMBO, Gaetano
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PALMISANO, Giuseppe, PALUMBO, Gaetano
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