Results 201 to 210 of about 156,051 (256)
Some of the next articles are maybe not open access.
Nanoelectronics devices: More CMOS, fusion CMOS and beyond CMOS
2009 IEEE Asian Solid-State Circuits Conference, 2009We are facing several difficulties with shrinking LSI chips, such as leakage currents/power consumption, variability, huge costs in R&D and production. Major semiconductor market will be absolutely dependent on further shrinking of Si CMOS transistors with improving transistor structures and lowering drive voltage, increasing wafer diameter and 3D ...
openaire +1 more source
Lab-on-CMOS: Integrating microfluidics and electrochemical sensor on CMOS
2011 6th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2011This paper introduces an integration process capable of merging an electrochemical CMOS chip with a microfluidic structure to bring the performance benefits of on-CMOS sensors to lab-on-chip platforms. This new approach embeds a CMOS die into a carrier chip and provides a planar surface that supports complex microfluidic channels beyond the dimensions ...
Yue Huang, Andrew J. Mason
openaire +1 more source
CMOS is dead … long live CMOS!
2007 IEEE Hot Chips 19 Symposium (HCS), 2007This article consists of a collection of slides from the author's conference presentation on the future of CMOS technologies. Some of the specific topics discussed include: the market for CMOS scaling; design considerations for materials plus CMOS scaling; the future that considers devices plus materials plus CMOS scaling; and new areas of future chip ...
openaire +1 more source
A CMOS fuse for safe release of CMOS-MEMS devices
2017 IEEE SENSORS, 2017This paper reports a safe release mechanism for MEMS devices fabricated using plasma etching based dry processes. The proposed smart fuse is particularly designed for CMOS-MEMS devices where inherent CMOS thin films are used as structural materials. Properly designed polysilicon heater sandwiched between CMOS layers is the critical element of the fuse.
Peng Qu, Hongwei Qu
openaire +2 more sources
IEEE Journal of Solid-State Circuits, 2005
A direct-conversion ultra-wideband (UWB) transceiver for Mode 1 OFDM applications employs three resonant networks and three phase-locked loops. Using a common-gate input stage, the receiver allows direct sharing of the antenna with the transmitter. Designed in 0.13-/spl mu/m CMOS technology, the transceiver provides a total gain of 69-73 dB and a noise
Behzad Razavi +8 more
openaire +2 more sources
A direct-conversion ultra-wideband (UWB) transceiver for Mode 1 OFDM applications employs three resonant networks and three phase-locked loops. Using a common-gate input stage, the receiver allows direct sharing of the antenna with the transmitter. Designed in 0.13-/spl mu/m CMOS technology, the transceiver provides a total gain of 69-73 dB and a noise
Behzad Razavi +8 more
openaire +2 more sources
Implementation of CMOS oscillator for CMOS SAW resonator
2016 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2016This work presents a design and measurement of pierce oscillator circuit for microelectromechanical system (MEMS) SAW resonator. The pierce oscillator circuit was fabricated using MIMOS 0.35um CMOS technology process. The pierce oscillator circuit provides gain to offset the losses of the resonator.
Jamilah Karim, Anis Nurashikin Nordin S.
openaire +1 more source
Generalised CMOS---a technology independent CMOS IC design style
Proceedings of the 22nd ACM/IEEE conference on Design automation - DAC '85, 1985A CMOS IC design methodology is presented which allows a single design representation, captured at the symbolic level, to be implemented in different classes of CMOS fabrication technologies such as N-well, P-well, twin-well, and SOI. Extensive use is made of CAD tools to achieve automatic conversion from the technology-independent representation into ...
openaire +2 more sources
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044), 2002
The VLSI industry is accelerating towards the end of scaling (bulk) CMOS. Near its scaling limit, a CMOS transistor could have a channel length of about 25 nm, a switching speed about three times as fast as a device of 100-nm channel length, and an f/sub T/ of about 250 GHz.
openaire +2 more sources
The VLSI industry is accelerating towards the end of scaling (bulk) CMOS. Near its scaling limit, a CMOS transistor could have a channel length of about 25 nm, a switching speed about three times as fast as a device of 100-nm channel length, and an f/sub T/ of about 250 GHz.
openaire +2 more sources
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 2005
B. Courtoi, Michael R. B. Forshaw
openaire +2 more sources
B. Courtoi, Michael R. B. Forshaw
openaire +2 more sources