Results 201 to 210 of about 47,494 (264)

Nanoscale CMOS

Proceedings of the IEEE, 1999
P M Solomon, J J Welser, D J Frank
exaly   +3 more sources

Graphene for CMOS and Beyond CMOS Applications

Proceedings of the IEEE, 2010
Owing in part to complementary metal-oxide-semiconductor (CMOS) scaling issues, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide a solution beyond the 22-nm node. Single and few layers of carbon sheets (graphene) have been fabricated by a variety of techniques including mechanical ...
Sanjay Kumar Banerjee, Leonard Franklin Register, Emanuel Tutuc, Dipanjan Basu, Seyoung Kim, Dharmendar Reddy, Allan H. MacDonald   +6 more
openaire   +3 more sources

A CMOS CCII+

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems, 2002
A novel CMOS CCII is presented which provides a voltage transfer error better than /spl plusmn/0.1 dB with resistances greater than 25 /spl Omega/. Moreover, the resistance at terminal X is as low as 0.3 /spl Omega/. Thanks to its simple topology, the circuit is particularly suitable as input stage of current feedback operational amplifiers and current
Giuseppe Di Cataldo, Giuseppe Palmisano, Gaetano Palumbo   +2 more
openaire   +2 more sources

CMOS clamped-swing logic (CMOS CSL) and CMOS differential clamped-swing logic (CMOS DCSL)

[1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems, 2003
Two new static CMOS logic circuits called the CMOS clamped-swing logic and the CMOS differential clamped-swing logic are proposed and analyzed. In these two new logic circuits, the internal circuit used to realize the logic functions has a small voltage swing, whereas the output signal has a normal swing compatible with other CMOS logic. Both new logic
H.-Y. Huang, C.-Y. Wu
openaire   +1 more source

Alternative CMOS or alternative to CMOS?

Microelectronics Reliability, 2001
Abstract We point out the main issues to address in order to investigate and push the limits of CMOS technology. The demand for low voltage, low power and high performance are the great challenges for engineering of sub-0.10 μm gate length devices. The possible solutions are reviewed through the issues in gate/channel and substrate, source and drain ...
openaire   +2 more sources

Mitigating defective CMOS to Non-CMOS vias in CMOS/Molecular memories

10th IEEE International Conference on Nanotechnology, 2010
CMOS/Molecular (CMOL) memory is one of the emerging memory technologies that promises increased data storage, reduced power consumption and minimized fabrication complexity. The fabrication of these memories is based on the stacking of non-CMOS-based memory cell array on the top of CMOS-based peripheral circuits.
Nor Zaidi Haron, Said Hamdioui
openaire   +1 more source

Nanoelectronics devices: More CMOS, fusion CMOS and beyond CMOS

2009 IEEE Asian Solid-State Circuits Conference, 2009
We are facing several difficulties with shrinking LSI chips, such as leakage currents/power consumption, variability, huge costs in R&D and production. Major semiconductor market will be absolutely dependent on further shrinking of Si CMOS transistors with improving transistor structures and lowering drive voltage, increasing wafer diameter and 3D ...
openaire   +1 more source

Lab-on-CMOS: Integrating microfluidics and electrochemical sensor on CMOS

2011 6th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2011
This paper introduces an integration process capable of merging an electrochemical CMOS chip with a microfluidic structure to bring the performance benefits of on-CMOS sensors to lab-on-chip platforms. This new approach embeds a CMOS die into a carrier chip and provides a planar surface that supports complex microfluidic channels beyond the dimensions ...
Yue Huang, Andrew J. Mason
openaire   +1 more source

CMOS is dead … long live CMOS!

2007 IEEE Hot Chips 19 Symposium (HCS), 2007
This article consists of a collection of slides from the author's conference presentation on the future of CMOS technologies. Some of the specific topics discussed include: the market for CMOS scaling; design considerations for materials plus CMOS scaling; the future that considers devices plus materials plus CMOS scaling; and new areas of future chip ...
openaire   +1 more source