Results 191 to 200 of about 156,051 (256)

Porous Ultralow‐κ sp2‐Bonded Boron Nitride Thin Films as Copper Diffusion Barriers

open access: yesAdvanced Science, EarlyView.
Porous sp2‐bonded boron nitride (p‐BN) thin films with an ultralow dielectric constant (κ = 1.77) are directly grown on Si substrates via RF magnetron sputtering. The films feature uniform nanopores (1.85 nm), high mechanical stability, hydrophobicity, and excellent Cu diffusion barrier performance even at 3 nm thickness, offering a promising solution ...
Caiyun Liu   +11 more
wiley   +1 more source

Optically Tunable Threshold Switching and Thermally Activated Transport in Planar Ag/MAPbI3 Thin Single‐Crystal Devices

open access: yesAdvanced Science, EarlyView.
Planar Ag/MAPbI3 thin single‐crystal halide perovskite devices show ultralow dark current and optically tunable threshold switching. Illumination enhances the polarity‐dependent hysteresis and shifts the switching voltage, whereas temperature‐dependent measurements reveal thermally activated, contact‐limited transport, underscoring the central role of ...
Ofelia Durante   +16 more
wiley   +1 more source

Neuromorphic Optical Tracking and Imaging of Randomly Moving Targets Through Dynamic Dense Scattering Media

open access: yesAdvanced Science, EarlyView.
Vision begins not with images but with change: the retina fires only when something moves, handing the brain a stream of spikes. A neuromorphic imaging system adopts the same strategy—an event sensor that sees like the retina, a spiking network that thinks like the brain—to track and reconstruct fully randomly moving targets through tissue (phantom ...
Ning Zhang, Arto Nurmikko
wiley   +1 more source

Miniaturization of CMOS [PDF]

open access: yesMicromachines, 2019
When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along ...
Junjie Li, Wang Guilei, Jinbiao Liu
exaly   +6 more sources
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Nanoscale CMOS

Proceedings of the IEEE, 1999
P M Solomon, J J Welser, D J Frank
exaly   +3 more sources

Graphene for CMOS and Beyond CMOS Applications

Proceedings of the IEEE, 2010
Owing in part to complementary metal-oxide-semiconductor (CMOS) scaling issues, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide a solution beyond the 22-nm node. Single and few layers of carbon sheets (graphene) have been fabricated by a variety of techniques including mechanical ...
Sanjay Kumar Banerjee   +6 more
openaire   +3 more sources

A CMOS CCII+

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems, 2002
A novel CMOS CCII is presented which provides a voltage transfer error better than /spl plusmn/0.1 dB with resistances greater than 25 /spl Omega/. Moreover, the resistance at terminal X is as low as 0.3 /spl Omega/. Thanks to its simple topology, the circuit is particularly suitable as input stage of current feedback operational amplifiers and current
Giuseppe Di Cataldo   +2 more
openaire   +2 more sources

CMOS clamped-swing logic (CMOS CSL) and CMOS differential clamped-swing logic (CMOS DCSL)

[1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems, 2003
Two new static CMOS logic circuits called the CMOS clamped-swing logic and the CMOS differential clamped-swing logic are proposed and analyzed. In these two new logic circuits, the internal circuit used to realize the logic functions has a small voltage swing, whereas the output signal has a normal swing compatible with other CMOS logic. Both new logic
H.-Y. Huang, C.-Y. Wu
openaire   +1 more source

Alternative CMOS or alternative to CMOS?

Microelectronics Reliability, 2001
Abstract We point out the main issues to address in order to investigate and push the limits of CMOS technology. The demand for low voltage, low power and high performance are the great challenges for engineering of sub-0.10 μm gate length devices. The possible solutions are reviewed through the issues in gate/channel and substrate, source and drain ...
openaire   +2 more sources

Mitigating defective CMOS to Non-CMOS vias in CMOS/Molecular memories

10th IEEE International Conference on Nanotechnology, 2010
CMOS/Molecular (CMOL) memory is one of the emerging memory technologies that promises increased data storage, reduced power consumption and minimized fabrication complexity. The fabrication of these memories is based on the stacking of non-CMOS-based memory cell array on the top of CMOS-based peripheral circuits.
Nor Zaidi Haron, Said Hamdioui
openaire   +1 more source

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