Results 281 to 290 of about 74,167 (345)

Scalable Reverse Converters for the Moduli Set {2n+1−1,2n−1,2n−1−1}$$ \left\{{2}^{n+1}-1,{2}^n-1,{2}^{n-1}-1\right\} $$ (n$$ n $$ Even)

International Journal of Circuit Theory and Applications, EarlyView.
This work explores the conversion from residues to binary representation in RNS using the Chinese remainder theorem (CRT) or mixed radix conversion (MRC) algorithms. The proposed approach relocates CRT multiplicative inverses to the arithmetic stage without extra cost, improving scalability while achieving speedups over state‐of‐the‐art MRC ...
Gabriel B. M. Fernandes, Hector Pettenghi, Lucas R. Kieslich   +2 more
wiley   +1 more source

Sub-THz communication systems: pushing the capabilities of silicon. [PDF]

Commun Eng
Gruber J, Alotaibi H, Tabatabavakili A, Chen L, Aghasi H, Naghavi SMH, Afshari E.   +6 more
europepmc   +1 more source

A subnanolitre tetherless optoelectronic microsystem for chronic neural recording in awake mice. [PDF]

Nat Electron
Lee S, Ghajari S, Sadeghi S, Zheng Y, Zahr H, Cortese AJ, Gu W, Choe K, Mok A, Wallace M, Jiao R, Wu C, Werth JC, Fan W, Mogalipuvvu P, Park JU, Zhao S, Smart C, Cleland TA, Warden MR, Lammerding J, Wang T, Goldberg JH, McEuen PL, Xu C, Molnar AC.   +25 more
europepmc   +1 more source

Nanophotonic waveguide chip-to-world beam scanning. [PDF]

Nature
Saha M, Wen YH, Greenspon AS, Zimmermann M, Palm KJ, Witte A, Goh YM, Li C, Bumstead J, Schädler K, Fortin R, Dong M, Leenheer AJ, Clark G, Gilbert G, Eichenfield M, Englund D.   +16 more
europepmc   +1 more source

Band Engineering and Structural-Geometrical Engineering in 2D/3D van der Waals Heterostructures for Advanced Photodetection and Intelligent Sensing. [PDF]

Nanomicro Lett
Yang M, Gong K, Cui Y, Liu S, Li G, Lin S.   +5 more
europepmc   +1 more source

Volatile and non-volatile nano-electromechanical switches fabricated in a CMOS-compatible silicon-on-insulator foundry process. [PDF]

Microsyst Nanoeng
Li Y, Bleiker SJ, Worsey E, Dagon M, Edinger P, Takabayashi AY, Quack N, Verheyen P, Bogaerts W, Gylfason KB, Pamunuwa D, Niklaus F.   +11 more
europepmc   +1 more source

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

, 1977
D. S. Woo
openalex   +1 more source

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Modeling Latch-Up in CMOS Integrated Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1982
Latch-up is a common problem in CMOS integrated circuits. The modeling of latch-up with circuit simulation programs is addressed in this paper. The general features of a lumped element latch-up model are discussed along with a step-by-step approach to the component determination of the model.
Donald B. Estreich, Robert W. Dutton
exaly   +2 more sources