Results 61 to 70 of about 74,167 (345)
Generic logic block based on bias-gated 2D MoS2 transistors
Nature CommunicationsIntegrating two-dimensional (2D) semiconductors and CMOS technology is a promising pathway for next-generation integrated circuits. However, the implementation of this strategy is hindered by the limited polarity modulation of 2D semiconductors and the ...
Xiaofu Wei +10 more
doaj +1 more source
A self‐biased and all‐in‐one voltage and current reference
Electronics Letters, 2021 This Letter presents a high‐performance self‐biased and all‐in‐one voltage and current reference without BJT and V–I converter exploiting the zero‐temperature‐coefficient point of the N‐type MOSFET.
Yuanfei Wang +4 more
doaj +1 more source
A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD-CP Noise Is not multiplied by N^2 [PDF]
, 2009 This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2
Bohsali, Mounhir +3 more
core +3 more sources
High-Performance Charge Pump Regulator with Integrated CMOS Voltage Sensing Control Circuit [PDF]
, 2023 Chan‐Soo Lee +5 more
openalex +1 more source
Advanced Functional Materials, EarlyView.This study demonstrates that memristors can replace conventional 2T–1C driving circuits with simplified 1T–1 m architectures by exploiting resistance switching. With ultra‐low switching voltages (< ±0.2 V) and multi‐level resistance states, the memristors precisely control the current injected into organic light‐emitting diodes (OLEDs).
Dong Hyun Kim +6 more
wiley +1 more source
Reducing MOSFET 1/f Noise and Power Consumption by "Switched Biasing" [PDF]
, 2000 Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the switched biasing technique ...
Gierkink, Sander L.J. +3 more
core +2 more sources
Exploring Pb‐Chelation Chemistry in the Crystallization Dynamics of Halide Perovskites
Advanced Functional Materials, EarlyView.A mechanism of how Pb‐chelation chemistry governs coordination geometry and initial nucleation behavior at the precursor level of halide perovskite, by regulating the deprotonation state of a chelating additive, is elucidated. This allows for innovative reaction‐system design principles that promote coherent growth while suppressing defect formation in
Byeong Jun Kim +13 more
wiley +1 more source
Micromachines, 2019 When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized.
Henry H. Radamson +15 more
doaj +1 more source
Photodetection in silicon beyond the band edge with surface states [PDF]
, 2007 Silicon is an extremely attractive material platform for integrated optics at telecommunications wavelengths, particularly for integration with CMOS circuits.
Baehr-Jones, T. +2 more
core +3 more sources
Advanced Functional Materials, EarlyView.Field‐free spin‐orbit torque domain‐wall synapses integrated with stochastic MTJ neurons enable compact hardware Boltzmann machines. Leveraging intrinsic stochasticity and multi‐level conductance, the system achieves efficient probabilistic learning with high accuracy, demonstrating a scalable spintronic platform for energy‐efficient edge AI.
Aijaz H. Lone +8 more
wiley +1 more source