Results 191 to 200 of about 3,033 (258)
Device to Circuit Co-Design Utilizing High-Performance PEALD Indium-Gallium-Zinc Oxide Thin-Film Transistor Enabling Technology Node Scaling in Monolithic 3D Systems. [PDF]
Wang W +11 more
europepmc +1 more source
2D Materials Powering Neuromorphic Intelligence. [PDF]
Kazmi J +9 more
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System-level integration of halide perovskite optoelectronics for its commercial deployment. [PDF]
Yang W +9 more
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Digital OTAs: Conventional Designs Versus Emerging Concept
Akbari M, Covi E, Gibertini P.
europepmc +1 more source
Optimized NCFET-based approximate multiplier for energy-aware image applications. [PDF]
Srinivas MBR, Elango K.
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Energy efficient approximate compressor architectures for high performance image multiplication in CNTFET technology. [PDF]
Foroutan P, Navi K.
europepmc +1 more source
A 0.6-V All-Digital Temperature Sensor with Reduced Supply Sensitivity. [PDF]
Zhou H, Wang Y, Xie S.
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IEE Proceedings, Part G: Circuits, Devices and Systems, 1990
We review the main difficulties and advantages in developing CMOS ternary circuits. In addition to employing multiple power sources and multiple thresholds, we describe a new theory of transmission functions for designing CMOS ternary logic circuits. It can explain the main CMOS ternary circuits proposed previously.
X W Wu
exaly +2 more sources
We review the main difficulties and advantages in developing CMOS ternary circuits. In addition to employing multiple power sources and multiple thresholds, we describe a new theory of transmission functions for designing CMOS ternary logic circuits. It can explain the main CMOS ternary circuits proposed previously.
X W Wu
exaly +2 more sources
IEEE Journal of Solid-State Circuits, 1984
A structure of dynamic CMOS logic based on the direct interconnection of p-channel logic and n-channel logic dynamic gates is reported. Prevention of glitches and other circuit problems are discussed. Application to a 16-bit parallel-adder design resulted in improved speed as well as important savings in layout area when compared to standard static ...
V Friedman
exaly +2 more sources
A structure of dynamic CMOS logic based on the direct interconnection of p-channel logic and n-channel logic dynamic gates is reported. Prevention of glitches and other circuit problems are discussed. Application to a 16-bit parallel-adder design resulted in improved speed as well as important savings in layout area when compared to standard static ...
V Friedman
exaly +2 more sources
Current-mode CMOS multiple-valued logic circuits
IEEE Journal of Solid-State Circuits, 1994Current-mode CMOS circuits are receiving increasing attention. Current-mode CMOS multiple-valued logic circuits are interesting and may have applications in digital signal processing and computing. In this paper we review several of the current-mode CMOS multiple-valued logic (MVL) circuits that we have studied over the past decade.
K W Current
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