Results 201 to 210 of about 3,033 (258)

Testing of zipper CMOS logic circuits

IEEE International Symposium on Circuits and Systems, 1990
A method for testing zipper CMOS circuits is presented. A gate-level model for the circuit is derived, and a single stuck-at fault test set for the model is obtained. Vectors are rearranged in the test set so that it can be used to detect single stuck-open and stuck-on faults in addition to stuck-at faults in the zipper CMOS circuit.
Qiao Tong, Niraj K. Jha
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A global optimization tool for CMOS logic circuits

ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357), 2003
Transistor sizing has been proved to be a very efficient technique for improving the performance of CMOS logic circuits in terms of both speed and power consumption. In this paper, new simple and accurate delay and power models are proposed: these models are integrated with time efficient algorithms for the transistor size optimization of large ...
DELAURENTI M., GRAZIANO, MARIAGRAZIA, MASERA, Guido, PICCININI G., M. ZAMBONI M.   +4 more
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Multiple fault detection in CMOS logic circuits

Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors, 2003
The possibility of using a single stuck-at fault test set to detect multiple faults and their combinations is studied. It is shown that a single stuck-at fault test set can detect single and multiple self-feedback bridging faults and combinations of feedback bridging, input bridging, and stuck-on faults when current monitoring is done.
Ding Lu, Carol Q. Tong
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Delay Modeling of CMOS/CPL Logic Circuits

2005 IEEE International Symposium on Circuits and Systems, 2005
Effective optimization methods aimed at achieving maximal speeds in single-technology logic circuits are widely available but systematic ways suitable for circuits involving mixtures of logic families are not. The combination of standard CMOS with CPL (complementary pass-transistor logic) is examined with an eye to finding the best structure and the ...
Yuanzhong Wan, Maitham Shams
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Design of fail-safe CMOS logic circuits

[1991] Proceedings. First Great Lakes Symposium on VLSI, 2002
Design techniques to make CMOS logic circuits fail-safe are reported. The set of transistor stuck-on and stuck-open faults, signal lines stuck-at faults, and bridging faults is partitioned into two classes of faults. Fail-safe property is maintained for multiple faults within a class. Limited fault tolerance capability is introduced as a by-product. >
V. Bobin, Sterling R. Whitaker
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H-tree CMOS logic circuit

2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Programmable routing networks and configurable logic blocks (CLB) achieve configurable computing of nowadays. This study proposed a novel H-tree configurable circuit. The 10-transistor (5P5N) CMOS version H-tree logic gate can generate AOI22, OAI22, AOI21, OAI21, NAND3, NAND2, NOR3, NOR2 and INV functions.
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Adiabatic-CMOS/CMOS-adiabatic logic interface circuit

International Journal of Electronics, 2000
This paper describes the design of an adiabatic-CMOS/CMOS-adiabatic logic interface circuit for a group of low-power adiabatic logic families with a similar clocking scheme. The circuit provides interfacing between several recently proposed low-power adiabatic logic circuits and traditional digital CMOS circuits. One advantage of this design is that it
K. T. Lau, W. Y. Wang, K. W. Ng
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Regenerative logic circuits with CMOS transistors

International Journal of Electronics, 1985
ABSTRACT Logic circuits with transfer characteristics in the form of hysteresis, proposed in the paper, consist of two stages. The input stage is a standard CMOS logic circuit (inverter, NAND or NOR); the output stage is a simple flip-flop. The flip-flop consists of two inverters and one pair of CMOS transistors functioning as a resistor.
B. L. DOKIĆ, Z. V. BUNDALO
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Resistorless Bi-CMOS logic circuit

IEEE International Symposium on Circuits and Systems, 2002
A logic circuit design which combines bipolar emitter coupled logic (ECL) and CMOS technology with extremely low power consumption and low propagation delay is introduced. The calculated and the simulated results show that the power-speed product is 12.5 P-J which is 35 P-J less than the conventional Motorola ECL-10 k.
H. Javan, H. Chamas
openaire   +1 more source

CMOS regenerative logic circuits

Microelectronics Journal, 1983
New solutions of inverter, NAND and NOR logic circuits with hysteresis transfer characteristic (Schmitt triggers) consisting of three standard CMOS logic circuits and one resistor are described in this paper. The input circuit determines the logic function of a Schmitt trigger and the other two are connected in an inverter configuration.
openaire   +1 more source