Results 211 to 220 of about 3,033 (258)

Quaternary CMOS Combinational Logic Circuits

2009 International Conference on Information and Multimedia Technology, 2009
Good Characteristics and advantages of multi-valued logic (MVL) electronic systems and circuits are created great interest for its practical implementation. This paper presents voltage mode quaternary CMOS circuit design using 90nm technology. Basic gates such as quaternary inverter, NMAX, NMIN and Quaternary multiplexer are designed and simulated. Low
Vasundara Patel K.S., K.S. Gurumurthy
openaire   +1 more source

Abacus logic and its CMOS circuits

International Journal of Electronics, 1989
Decimal codes are proposed for biquinary (‘2–5’) mixed-valued signals, i.e. abacus logic, and a procedure for designing CMOS quinary circuits based on transmission function theory. Some 2–5 mixed-valued circuits for both combinational and sequential logic are designed and simulated by using SPICE2G5.
XIEXIONG CHEN, XUNWEI WU
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CMOS integrated circuits for multivalued logic

International Journal of Electronics, 1985
ABSTRACT The use of CMOS integrated circuits in the design of multivalued logic systems is extended. Circuit design of basic quaternary operators (inverters, NAND, NOR, cycling and inverse cycling gates) is presented. These basic quaternary operators can be used as building blocks in four-valued digital systems.
H. T. MOUFTAH, K. C. SMITH
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Adiabatic dynamic CMOS logic circuit

Electronics and Communications in Japan (Part II: Electronics), 2000
In this study, an adiabatic dynamic CMOS logic (ADCL) circuit for superlow power consumption is proposed and the effectiveness of the circuit is proven by circuit analysis, computer simulation, and experiments using discrete devices. The mutual interconnect between the logic circuits is as easy as that of CMOS circuits and the power consumption of the ...
Kazukiyo Takahashi, Mitsuru Mizunuma
openaire   +1 more source

Modeling and simulation of combinational CMOS logic circuits by ANFIS

Microelectronics Journal, 2010
In this paper, application of adaptive neuro-fuzzy inference system (ANFIS) in modeling of CMOS logic gates as a tool in designing and simulation of CMOS logic circuits is presented. Structures of the ANFIS are developed and trained in MATLAB 7.0.4 program. We have used real hardware data for training the ANFIS network.
Mohsen Hayati, Abbas Rezaei, Majid Seifi, Ali Naderi   +3 more
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New logic circuits consisting of quantum dots and CMOS

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005., 2006
This paper provides hybrid circuits which consist of RTD based quantum dot structure and CMOS circuitry. Several Boolean logics, OR, AND, XOR, MCF (majority carrier function), and full adder are implemented using the hybrid circuits. Combining strong points of each of quantum dot structure and CMOS, the hybrid circuits represent superior characteristic
Woo Hyung Lee, Pinaki Mazumder
openaire   +1 more source

Logic testing of bridging faults in CMOS integrated circuits

IEEE Transactions on Computers, 1998
We describe a system for simulating and generating accurate tests for bridging faults in CMOS ICs. After introducing the Primitive Bridge Function, a characteristic function describing the behavior of a bridging fault, we present the Test Guarantee Theorem, which allows for accurate test generation for feedback bridging faults via topological analysis ...
Brian Chess, Tracy Larrabee
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Robust testing of CMOS logic circuits

Computers & Electrical Engineering, 1989
Abstract It is well-known that two-pattern tests, which are required to detect stuck-open faults in CMOS logic circuits, can be invalidated if circuit delays have been ignored in their derivation. Furthermore, for certain CMOS circuits a robust test set, which remains valid in the presence of arbitrary circuit delays, may not exist. However, for most
openaire   +1 more source

Memristor−CMOS Hybrid Integrated Circuits for Reconfigurable Logic

Nano Letters, 2009
Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS.
Qiangfei, Xia, Warren, Robinett, Michael W, Cumbie, Neel, Banerjee, Thomas J, Cardinali, J Joshua, Yang, Wei, Wu, Xuema, Li, William M, Tong, Dmitri B, Strukov, Gregory S, Snider, Gilberto, Medeiros-Ribeiro, R Stanley, Williams   +12 more
openaire   +2 more sources

Voltage comparator circuits for multiple-valued CMOS logic

Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic, 2003
A new voltage-mode comparator circuit for use in CMOS multiple-valued logic circuits is introduced. Existing comparator circuits for this application use static current or clocking and thus consume static power or clocking power. In order to reduce these power requirements, we have examined static circuit designs that eliminate DC current paths when ...
Yongjian Brandon Guo, K. Wayne Current
openaire   +1 more source