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On the design of robust testable CMOS combinational logic circuits
[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers, 2003The authors propose an integrated approach to the design of combinational logic circuits in which stuck-open faults and path delay faults are detectable by robust tests that detect modeled faults independent of the delays in the circuit under test. They demonstrate that the proposed designs and tests guarantee the design of CMOS logic circuits in which
Sandip Kundu, Sudhakar M. Reddy
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Design of current steering logic CMOS circuit
Microelectronics Journal, 2023Jiaming Shen, Fangjun Liu, Jizhong Shen
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Signed-digit CMOS (SD-CMOS) Logic Circuits with Dynamic Operation
35th International Symposium on Multiple-Valued Logic (ISMVL'05), 2005This paper proposes a design for signed-digit CMOS (SD-CMOS) basic circuits, such as a driver circuit, an inverter circuit, and a full-adder circuit, and describes a parallel multiplier circuit capable of high-speed operation with a time of about 10 nsec independent of the bit length.
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Testing for multiple faults in domino-CMOS logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988The problem of multiple faults detection in domino-CMOS logic circuits is considered. The multiple faults can be of the stuck-open and stuck-on types. It is shown that a multiple fault in the domino-CMOS circuit can be mapped to a multiple stuck-at fault in its gate-level model.
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Multiple valued logic: current-mode CMOS circuits
[1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic, 2002Several of the current-mode CMOS multiple-valued-logic (MVL) circuits that the author has studied over the past decade are reviewed. These circuits include a simple current threshold comparator, MVL encoders and decoders, quaternary threshold logic full adders (QFAs), MVL latches, latched QFA circuits, and analog-to-quaternary converter circuits. >
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Logic synthesis of race-free asynchronous CMOS circuits
IEEE Journal of Solid-State Circuits, 1991A synthesis method for generating race-free asynchronous CMOS circuits that are independent of the internal and output delays is presented. The design method is based on the properties of the negative gates. An inertial delay is associated with each negative gate in a CMOS circuit. Such a gate model is quite realistic. The basic principle of the method
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Recognition of logic blocks in CMOS circuits
2017A Prolog based approach towards the recognition of logic functional blocks in CMOS circuits is described in this thesis. A transistor level description of the circuit is assumed to be available. Predefined gates and logic blocks are extracted from such a description.
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2016
For a few decades, CMOS has been well known for a quite efficient design methodology. With its unique characteristics, CMOS logic has been most commonly used for low voltage operation. Although in many cases CMOS logic can achieve more robust performance than pass-transistor logic and Dynamic Logic counterparts, due to the fact that the delay o f low ...
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For a few decades, CMOS has been well known for a quite efficient design methodology. With its unique characteristics, CMOS logic has been most commonly used for low voltage operation. Although in many cases CMOS logic can achieve more robust performance than pass-transistor logic and Dynamic Logic counterparts, due to the fact that the delay o f low ...
openaire +1 more source