Results 41 to 50 of about 3,011 (245)

Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits [PDF]

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2009
SUMMARY A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their
Taichi Ogawa, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya   +3 more
openaire   +2 more sources

Neuromorphic Electronics for Intelligence Everywhere: Emerging Devices, Flexible Platforms, and Scalable System Architectures

Advanced Materials, EarlyView.
The perspective presents an integrated view of neuromorphic technologies, from device physics to real‐time applicability, while highlighting the necessity of full‐stack co‐optimization. By outlining practical hardware‐level strategies to exploit device behavior and mitigate non‐idealities, it shows pathways for building efficient, scalable, and ...
Kapil Bhardwaj, Roshni Satheesh Babu, Yuxin Xia, Eva Bestelink, Radu Sporea, Nikos Hastas, Ioannis Zeimpekis, Dimitra G. Georgiadou, Sayani Majumdar   +8 more
wiley   +1 more source

Low power domino logic circuits in deep-submicron technology using CMOS

Engineering Science and Technology, an International Journal, 2018
Leakage power and propagation delay are the two major challenges in designing CMOS VLSI circuits, in deep sub-micron technology. This paper proposes a novel technique: Foot Driven Stack Transistor Domino Logic (FDSTDL) for designing CMOS domino logic ...
Sandeep Garg, Tarun Kumar Gupta
doaj   +1 more source

Optoelectronic Nanofluidic Neural Networks for Ionic Computing

Advanced Materials, EarlyView.
An ion‐based optoelectronic nanofluidic memristor enables neuromorphic computing in aqueous environments. With tunable ionic memory and multimodal synaptic plasticity, it realizes densely connected ionic neural networks capable of image classification, motion prediction, logic computation, and real‐time in‐sensor computing, advancing fully connected ...
Yaxin Huang, Zhiyuan Du, Changjin Wu, Binglin Zeng, Yingnan Cao, Mingliang Li, Liren Zhang, Qingxin Guo, Chao Huang, Can Li, Jinyao Tang   +10 more
wiley   +1 more source

MINI Logic 1-Bit Adder: A Comparison with Hybrid NMOS-Memristor-Logic Styles Using Ta2O5/Al2O3 Based RRAM Device

Advances in Electrical and Computer Engineering
This study addresses the demand for more efficient logic circuits by focusing on reducing area, power consumption, and delay. As conventional CMOS technology faces scaling and efficiency limitations, integrating emerging memory technologies like ...
NITHYA, N., PARAMASIVAM, K.
doaj   +1 more source

Compact FeFET Circuit Building Blocks for Fast and Efficient Nonvolatile Logic-in-Memory

IEEE Journal of the Electron Devices Society, 2020
Due to their CMOS compatibility, hafnium oxide based ferroelectric field-effect transistors (FeFET) gained remarkable attention recently, not only in the context of nonvolatile memory applications but also for being an auspicious candidate for novel ...
Evelyn T. Breyer, Halid Mulaosmanovic, Jens Trommer, Thomas Melde, Stefan Dunkel, Martin Trentzsch, Sven Beyer, Stefan Slesazeck, Thomas Mikolajick   +8 more
doaj   +1 more source

Barrier‐Assisted Plasma Doping for Spatially Selective Resistance Engineering in MoS2 Transistors

Advanced Materials, EarlyView.
Barrier‐assisted NH3 plasma doping enables damage‐free, spatially selective carrier modulation in monolayer MoS2 transistors. An ultrathin pV3D3/Al2O3 protective‐dielectric stack acts as a chemical filter that allows NHx radicals to reach the MoS2 surface while blocking plasma damage. This process achieves a high electron concentration of 4.3 × 1013 cm−
Inseong Lee, Joonho Park, Seungsun Yoo, Seunghyun Yu, Mingu Kang, Seohak Park, Min Kyu Lee, Hyeongjin Lim, Dongyoung Kim, Kunwoo Roh, Sejin Kim, Kihyuk Kim, Wonbae Ahn, Kibum Kang, Yong‐Hoon Kim, Sung‐Yool Choi   +15 more
wiley   +1 more source

Average leakage current estimation of CMOS logic circuits [PDF]

Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, 2002
In a product engineering environment there is a need to know quickly the average standby current of an IC for various combinations of power supply and temperature. We present two techniques to do this estimation without resorting to involved simulations. We use a bottom-up methodology that propagates the effect of process variations to higher levels of
Pineda de Gyvez, J., Wetering, van der, E.   +1 more
openaire   +1 more source

Noise‐Tunable Memristor Enabling Programmable Probabilistic Neurons for Frequency‐Selective Time‐Series Signal Encoding

Advanced Materials, EarlyView.
Memristors offer tunable resistance and intrinsic instability, making them promising tunable noise sources. We propose a spiking‐rate‐programmable probabilistic neuron using a Ru/TaOx/Pt memristor, where resistance‐dependent noise enables frequency‐selective encoding.
Do Hoon Kim, Seoeun Jang, Hakseung Rhee, Min Gu Lee, Daehee Kim, Taewook Go, Woon Hyung Cheong, Hanchan Song, Kyung Min Kim   +8 more
wiley   +1 more source

A Universal van der Waals Tunneling Injector for Monolayer CMOS

Advanced Materials, EarlyView.
A universal van der Waals injector unlocks polarity‐flexible tunneling contacts for monolayer CMOS. SnSe2, an intrinsically degenerate 2D semiconductor, establishes polarity‐specific band alignments with both WSe2 and MoS2 channels, enabling steep switching, high on/off ratios, and a unified route to low‐power 2D logic.
Hanbin Cho, Jing Huang, Seonguk Yang, Subin Im, Sangwoo Park, Jeongin Yeo, Sungyeon Kim, Gilhwan Do, Wenxuan Zhu, Soobeom Shin, Jongwon Lee, Yongjoon Shin, Do‐Sun Lee, Hu Young Jeong, Tae‐Eon Park, Jun Kang, Kyungmin Ko, Joonki Suh   +17 more
wiley   +1 more source