Results 111 to 120 of about 8,692,712 (154)
Some of the next articles are maybe not open access.
Generalised CMOS---a technology independent CMOS IC design style
Proceedings of the 22nd ACM/IEEE conference on Design automation - DAC '85, 1985A CMOS IC design methodology is presented which allows a single design representation, captured at the symbolic level, to be implemented in different classes of CMOS fabrication technologies such as N-well, P-well, twin-well, and SOI. Extensive use is made of CAD tools to achieve automatic conversion from the technology-independent representation into ...
openaire +2 more sources
2004 Asia-Pacific Radio Science Conference, 2004. Proceedings., 2005
RF CMOS characteristics have been traditionally regarded as poorer than those of Si-bipolar and compound devices. However, recent aggressive downsizing of CMOS devices has improved their RF characteristics significantly and some of them have already exceeded some Si-bipolar and GaAs transistors.
openaire +1 more source
RF CMOS characteristics have been traditionally regarded as poorer than those of Si-bipolar and compound devices. However, recent aggressive downsizing of CMOS devices has improved their RF characteristics significantly and some of them have already exceeded some Si-bipolar and GaAs transistors.
openaire +1 more source
1983 International Electron Devices Meeting, 1983
This paper describes current status and future prospect of CMOS technology for VLSI circuit applications. Though requiring various improvements and optimizations, CMOS device structures and process steps remain to be rather conventional down to 1.2 µm, and real innovation or evolution is expected to come below 1.0 µm or in the sub-micron region.
S. Kohyama, J. Matsunaga, K. Hashimoto
openaire +1 more source
This paper describes current status and future prospect of CMOS technology for VLSI circuit applications. Though requiring various improvements and optimizations, CMOS device structures and process steps remain to be rather conventional down to 1.2 µm, and real innovation or evolution is expected to come below 1.0 µm or in the sub-micron region.
S. Kohyama, J. Matsunaga, K. Hashimoto
openaire +1 more source
1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1981
This paper will report on a bulk CMOS technology based on HMOS, affording such features as high resistivity P substrate diffused wells and 2μm channel length N and P channel devices. A 4K static RAM test vehicle using this approach has demonstrated 25ns access time and microwatt standby power.
K. Yu +4 more
openaire +1 more source
This paper will report on a bulk CMOS technology based on HMOS, affording such features as high resistivity P substrate diffused wells and 2μm channel length N and P channel devices. A 4K static RAM test vehicle using this approach has demonstrated 25ns access time and microwatt standby power.
K. Yu +4 more
openaire +1 more source
2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846), 2005
Previously, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology ...
openaire +1 more source
Previously, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology ...
openaire +1 more source
2011
In this chapter, we will first simulate a very simple 3D device. A long channel n-type MOSFET (NMOS) is the simplest 3D simulation case for unipolar devices, as it is merely an extension of a 2D simulation. There is no variation along the z direction so only two planes are needed to perform a 3D simulation.
Simon Li, Yue Fu
openaire +1 more source
In this chapter, we will first simulate a very simple 3D device. A long channel n-type MOSFET (NMOS) is the simplest 3D simulation case for unipolar devices, as it is merely an extension of a 2D simulation. There is no variation along the z direction so only two planes are needed to perform a 3D simulation.
Simon Li, Yue Fu
openaire +1 more source
1991
Complementary MOS (CMOS) is, by far, the technology of choice for the realization of integrated circuits on SOI substrates. This Chapter will compare CMOS processing on bulk silicon and on SOI wafers. Processing of both thin and thicker SOI films will be discussed.
openaire +1 more source
Complementary MOS (CMOS) is, by far, the technology of choice for the realization of integrated circuits on SOI substrates. This Chapter will compare CMOS processing on bulk silicon and on SOI wafers. Processing of both thin and thicker SOI films will be discussed.
openaire +1 more source
1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1983
Unlike NMOS technology, which has been relatively standardized by the industry, CMOS technology is currently much more varied in its methods of production. Presently, the following alternatives (and related issues) exist: bulk CMOS versus CMOS-SOS (cost, yield, performance), P-well versus N-well architecture (performance, latch-up, immunity, alpha ...
openaire +1 more source
Unlike NMOS technology, which has been relatively standardized by the industry, CMOS technology is currently much more varied in its methods of production. Presently, the following alternatives (and related issues) exist: bulk CMOS versus CMOS-SOS (cost, yield, performance), P-well versus N-well architecture (performance, latch-up, immunity, alpha ...
openaire +1 more source
2014
In this chapter the CMOS technologies used for design and fabrication of comparator test chips described in this book are introduced. The MOS transistor characteristics in nanometer CMOS are shown.
Bernhard Goll, Horst Zimmermann
openaire +1 more source
In this chapter the CMOS technologies used for design and fabrication of comparator test chips described in this book are introduced. The MOS transistor characteristics in nanometer CMOS are shown.
Bernhard Goll, Horst Zimmermann
openaire +1 more source
Sensors and Actuators A: Physical, 1993
Abstract Sensor design and fabrication using industrial IC technologies has the advantages of batch fabrication and on-chip interface circuitry. Sensors made by CMOS or bipolar IC technology have been demonstrated for magnetic, temperature and radiation measurands.
openaire +1 more source
Abstract Sensor design and fabrication using industrial IC technologies has the advantages of batch fabrication and on-chip interface circuitry. Sensors made by CMOS or bipolar IC technology have been demonstrated for magnetic, temperature and radiation measurands.
openaire +1 more source