Results 101 to 110 of about 8,692,712 (154)
Stacked 3-D Fin-CMOS Technology
IEEE Electron Device Letters, 2005 A stacked three-dimensional Fin-CMOS (SF-CMOS) technology has been proposed and implemented. The technology is based on a double-layer SOI wafer formed by performing two oxygen implants to form two single-crystal silicon films with isolation layer in ...
Shengdong Zhang, Xusheng Wu, P C H Chan
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CMOS technology trends and economics
IEEE Micro, 1992CMOS has become the mainstream IC technology. Extending well into the sub-0.1- mu m regime, its potential provides enormous chip complexities for integration of complete systems on one chip. A number of general trends in the development and manufacturing of CMOS technologies and ICs are discussed.
Armin W. Wieder, Franz Neppl
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Microelectronics Reliability, 2002
This paper presents a high performance RF CMOS technology with a complete portfolio of RF andbase band components for single-chip systems. Using an optimized0.13 lm CMOS topology, fT of 86 GHz and fmax of 73 GHz are obtained, in addition to a NFmin of 1.5 dB without ground-shielded signal pad.
Chun-Yen Chang 0002 +4 more
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This paper presents a high performance RF CMOS technology with a complete portfolio of RF andbase band components for single-chip systems. Using an optimized0.13 lm CMOS topology, fT of 86 GHz and fmax of 73 GHz are obtained, in addition to a NFmin of 1.5 dB without ground-shielded signal pad.
Chun-Yen Chang 0002 +4 more
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IBM Journal of Research and Development, 2000
The performance of integrated circuits has been improving exponentially for more than thirty years. During the next decade, the industry must overcome several technological challenges to sustain this remarkable pace of improvement. Challenges in lithography, transistor scaling, interconnections, circuit families, computer memory, and circuit design are
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The performance of integrated circuits has been improving exponentially for more than thirty years. During the next decade, the industry must overcome several technological challenges to sustain this remarkable pace of improvement. Challenges in lithography, transistor scaling, interconnections, circuit families, computer memory, and circuit design are
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Variability in nanoscale CMOS technology
Science China Information Sciences, 2011Moore’s Law technology scaling has improved VLSI performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore’s Law, a variety of challenges will need to be overcome. One of these challenges is management of process variation.
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Experimental Astronomy, 2006
An entry level overview of state-of-the-art CMOS detector technology is presented. Operating principles and system architecture are explained in comparison to the well-established CCD technology, followed by a discussion of important benefits of modern CMOS-based detector arrays.
Alan Hoffman +2 more
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An entry level overview of state-of-the-art CMOS detector technology is presented. Operating principles and system architecture are explained in comparison to the well-established CCD technology, followed by a discussion of important benefits of modern CMOS-based detector arrays.
Alan Hoffman +2 more
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Future of nano CMOS technology
2014 IEEE International Conference on Electron Devices and Solid-State Circuits, 2007Although silicon-based CMOS devices have dominated the integrated circuit applications over the past few decades, it is expected that the development of CMOS would reach its limits after the next decade because of the difficulties in downsizing and also some fundamental limits of MOSFETs.
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1998 IEEE International Reliability Physics Symposium Proceedings 36th Annual (Cat No 98CH36173) RELPHY-98, 1998
This paper is a review of the latchup phenomena in past and present CMOS technologies. Both static and transient characterization techniques are described, as well as process related solutions and layout ground rule constraints. Technology scaling implications are discussed in the context of latchup holding voltage/current and minimum N/sup +/ to P/sup
M.J. Hargrove +5 more
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This paper is a review of the latchup phenomena in past and present CMOS technologies. Both static and transient characterization techniques are described, as well as process related solutions and layout ground rule constraints. Technology scaling implications are discussed in the context of latchup holding voltage/current and minimum N/sup +/ to P/sup
M.J. Hargrove +5 more
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Technology Options for Beyond-CMOS
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017CMOS integrated circuit technology for computation is at an inflexion point. Although this is the technology which has enabled the semiconductor industry to make vast progress over the past 30-plus years, it is expected to see challenges going beyond the ten year horizon, particularly from an energy efficiency point of view.
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Magnetotransistor in CMOS technology
IEEE Transactions on Electron Devices, 1986An investigation of the magnetic-field sensitivity of a lateral double-base contact n-p-n magnetotransistor compatible with CMOS technology is reported. An approximate theoretical analysis of the sensitivity is made. Two physical mechanisms are considered: current deflection and injection modulation. The deflection mechanism is more significant.
R.S. Popovic, R. Widmer
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