Results 81 to 90 of about 8,692,712 (154)
Rad Tolerant CMOS Image Sensor Based on Hole Collection 4T Pixel Pinned Photodiode [PDF]
, 2012 1.4μm pixel pitch CMOS Image sensors based on hole collection pinned photodiode (HPD) have been irradiated with 60Co source. The HPD sensors exhibit much lower dark current degradation than equivalent commercial sensors using an Electron collection ...
Place, Sébastien +5 more
core +1 more source
A Novel Scheme for Fault-Tolerant And Higher Capacity Network on Chip
International Journal of Information and Communication Technology Research, 2010 As CMOS technology scales down, NoC (Network on Chip) gradually becomes the mainstream of onchip communication. In this paper we present a methodology to design fault-tolerant routing algorithms for regular direct interconnection networks.
Maryam Raiyat Aliabadi +2 more
doaj
Integrated circuits of self-scanning linear photodetectors in introscopy and tomography
Технологія та конструювання в електронній апаратурі, 2005 The results of designing and the characteristics of linear photosensitive devices (LPDs) based on active sensor cells and digital polling registers are presented.
V. L. Perevertaylo +4 more
doaj
Dynamic range optimisation of CMOS image sensors dedicated to space applications [PDF]
, 2007 Nowadays, CMOS image sensors are widely considered for space applications. Their performances have been significantly enhanced with the use of CIS (CMOS Image Sensor) processes in term of dark current, quantum efficiency and conversion gain.
Huger, Nicolas +5 more
core
Design and Implementation of a Hybrid SET-CMOS Based Sequential Circuits [PDF]
Журнал нано- та електронної фізики, 2012 Single Electron Transistor is a hot cake in the present research area of VLSI design and Microelectron-ics technology. It operates through one-by-one tunneling of electrons through the channel, utilizing the Coulomb blockade Phenomenon.
Anindya Jana +3 more
doaj
Ultra Low Power CMOS Technology
, 1991 This paper discusses the motivation, opportunities, and problems associated with implementing digital logic at very low voltages, including the challenge of making use of the available real estate in 3D multichip modules, energy requirements of very ...
Power Cmos Technology +3 more
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Design Low Power 130mW Pipeline ADC With Speed 80 MSPS 8-bit [PDF]
, 2009 This paper describes a pipeline analog-to-digital converter is implemented for high speed camera. In the pipeline ADC design, prime factor is designing operational amplifier with high gain so ADC have been high speed.
afandi, Hamzah
core
, 2011 In silicon bulk CMOS technology the variability of the device parameters is a key drawback that may be a limiting factor for further miniaturizing nodes. New nanoscale beyond-CMOS devices are being studied such as carbon nanotubes (CNTs).
García Almudéver, Carmen +1 more
core +1 more source
Influence of displacement damage dose on dark current distributions of irradiated CMOS image sensors [PDF]
Dark current increase distributions due to displacement damages are modeled using displacement damage dose concept. Several CMOS image sensors have been exposed to neutrons or protons and we have characterized their degradation in terms of dark current ...
Goiffon, Vincent +7 more
core
Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology
, 2014 Bulk-driven (BD) technique has been proposed to remedy the voltage swing limitation problem in modern CMOS technology. However, challenges exist when the CMOS technologies move to the nanometer-scale.
Yu, Haoran
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