Results 271 to 280 of about 7,600,943 (308)
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2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846), 2005
Previously, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology ...
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Previously, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology ...
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1991
Complementary MOS (CMOS) is, by far, the technology of choice for the realization of integrated circuits on SOI substrates. This Chapter will compare CMOS processing on bulk silicon and on SOI wafers. Processing of both thin and thicker SOI films will be discussed.
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Complementary MOS (CMOS) is, by far, the technology of choice for the realization of integrated circuits on SOI substrates. This Chapter will compare CMOS processing on bulk silicon and on SOI wafers. Processing of both thin and thicker SOI films will be discussed.
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Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 2004., 2005
Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology node,
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Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology node,
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2004 Asia-Pacific Radio Science Conference, 2004. Proceedings., 2005
RF CMOS characteristics have been traditionally regarded as poorer than those of Si-bipolar and compound devices. However, recent aggressive downsizing of CMOS devices has improved their RF characteristics significantly and some of them have already exceeded some Si-bipolar and GaAs transistors.
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RF CMOS characteristics have been traditionally regarded as poorer than those of Si-bipolar and compound devices. However, recent aggressive downsizing of CMOS devices has improved their RF characteristics significantly and some of them have already exceeded some Si-bipolar and GaAs transistors.
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1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1983
Unlike NMOS technology, which has been relatively standardized by the industry, CMOS technology is currently much more varied in its methods of production. Presently, the following alternatives (and related issues) exist: bulk CMOS versus CMOS-SOS (cost, yield, performance), P-well versus N-well architecture (performance, latch-up, immunity, alpha ...
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Unlike NMOS technology, which has been relatively standardized by the industry, CMOS technology is currently much more varied in its methods of production. Presently, the following alternatives (and related issues) exist: bulk CMOS versus CMOS-SOS (cost, yield, performance), P-well versus N-well architecture (performance, latch-up, immunity, alpha ...
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Beyond CMOS - benchmarking for future technologies
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012Sotomayor Torres, C.M. +5 more
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2008
Stacking metal-oxide semiconductor field-effect transistors on top of each other to form multilayer integrated circuits (ICs) is an effective way to reduce footprint and interconnect distance. In term of topology, stacked complementary metal-oxide semiconductor (CMOS) technologies can be classified into two major categories: One that has the active ...
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Stacking metal-oxide semiconductor field-effect transistors on top of each other to form multilayer integrated circuits (ICs) is an effective way to reduce footprint and interconnect distance. In term of topology, stacked complementary metal-oxide semiconductor (CMOS) technologies can be classified into two major categories: One that has the active ...
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CMOS active pixel image sensors fabricated using a 1.8-V, 0.25-μm CMOS technology
IEEE Transactions on Electron Devices, 1998E Crabbe
exaly
Upset hardened memory design for submicron CMOS technology
IEEE Transactions on Nuclear Science, 1996Michael Nicolaidis, R Velazco
exaly