Results 261 to 270 of about 7,600,943 (308)
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1983 International Electron Devices Meeting, 1983
This paper describes current status and future prospect of CMOS technology for VLSI circuit applications. Though requiring various improvements and optimizations, CMOS device structures and process steps remain to be rather conventional down to 1.2 µm, and real innovation or evolution is expected to come below 1.0 µm or in the sub-micron region.
S. Kohyama, J. Matsunaga, K. Hashimoto
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This paper describes current status and future prospect of CMOS technology for VLSI circuit applications. Though requiring various improvements and optimizations, CMOS device structures and process steps remain to be rather conventional down to 1.2 µm, and real innovation or evolution is expected to come below 1.0 µm or in the sub-micron region.
S. Kohyama, J. Matsunaga, K. Hashimoto
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Technology Options for Beyond-CMOS
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017CMOS integrated circuit technology for computation is at an inflexion point. Although this is the technology which has enabled the semiconductor industry to make vast progress over the past 30-plus years, it is expected to see challenges going beyond the ten year horizon, particularly from an energy efficiency point of view.
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Experimental Astronomy, 2006
An entry level overview of state-of-the-art CMOS detector technology is presented. Operating principles and system architecture are explained in comparison to the well-established CCD technology, followed by a discussion of important benefits of modern CMOS-based detector arrays.
Alan Hoffman +2 more
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An entry level overview of state-of-the-art CMOS detector technology is presented. Operating principles and system architecture are explained in comparison to the well-established CCD technology, followed by a discussion of important benefits of modern CMOS-based detector arrays.
Alan Hoffman +2 more
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Generalised CMOS---a technology independent CMOS IC design style
Proceedings of the 22nd ACM/IEEE conference on Design automation - DAC '85, 1985A CMOS IC design methodology is presented which allows a single design representation, captured at the symbolic level, to be implemented in different classes of CMOS fabrication technologies such as N-well, P-well, twin-well, and SOI. Extensive use is made of CAD tools to achieve automatic conversion from the technology-independent representation into ...
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Magnetotransistor in CMOS technology
IEEE Transactions on Electron Devices, 1986An investigation of the magnetic-field sensitivity of a lateral double-base contact n-p-n magnetotransistor compatible with CMOS technology is reported. An approximate theoretical analysis of the sensitivity is made. Two physical mechanisms are considered: current deflection and injection modulation. The deflection mechanism is more significant.
R.S. Popovic, R. Widmer
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2014
In this chapter the CMOS technologies used for design and fabrication of comparator test chips described in this book are introduced. The MOS transistor characteristics in nanometer CMOS are shown.
Bernhard Goll, Horst Zimmermann
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In this chapter the CMOS technologies used for design and fabrication of comparator test chips described in this book are introduced. The MOS transistor characteristics in nanometer CMOS are shown.
Bernhard Goll, Horst Zimmermann
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Sensors and Actuators A: Physical, 1993
Abstract Sensor design and fabrication using industrial IC technologies has the advantages of batch fabrication and on-chip interface circuitry. Sensors made by CMOS or bipolar IC technology have been demonstrated for magnetic, temperature and radiation measurands.
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Abstract Sensor design and fabrication using industrial IC technologies has the advantages of batch fabrication and on-chip interface circuitry. Sensors made by CMOS or bipolar IC technology have been demonstrated for magnetic, temperature and radiation measurands.
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1998
In this chapter, SOI CMOS technology is described. Starting from the evolution of SOI technology, various SOI substrate and isolation techniques are introduced. Then, a 0.25μm SOI CMOS fabrication processing sequence is described, followed by major SOI CMOS device structures.
James B. Kuo, Ker-Wei Su
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In this chapter, SOI CMOS technology is described. Starting from the evolution of SOI technology, various SOI substrate and isolation techniques are introduced. Then, a 0.25μm SOI CMOS fabrication processing sequence is described, followed by major SOI CMOS device structures.
James B. Kuo, Ker-Wei Su
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2004
In the 1940s the electronic history was marked by the invention of the transistor and only a decade after the first Integrated Circuit (IC) was realized. Nowadays, few decades after that invention, the CMOS Technology Platform is putting us in front of another major forefront: the capability to realize an entire system on a single piece of silicon, the
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In the 1940s the electronic history was marked by the invention of the transistor and only a decade after the first Integrated Circuit (IC) was realized. Nowadays, few decades after that invention, the CMOS Technology Platform is putting us in front of another major forefront: the capability to realize an entire system on a single piece of silicon, the
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2011
In this chapter, we will first simulate a very simple 3D device. A long channel n-type MOSFET (NMOS) is the simplest 3D simulation case for unipolar devices, as it is merely an extension of a 2D simulation. There is no variation along the z direction so only two planes are needed to perform a 3D simulation.
Simon Li, Yue Fu
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In this chapter, we will first simulate a very simple 3D device. A long channel n-type MOSFET (NMOS) is the simplest 3D simulation case for unipolar devices, as it is merely an extension of a 2D simulation. There is no variation along the z direction so only two planes are needed to perform a 3D simulation.
Simon Li, Yue Fu
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