Results 241 to 250 of about 7,631,832 (303)
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1983 International Electron Devices Meeting, 1983
This paper describes current status and future prospect of CMOS technology for VLSI circuit applications. Though requiring various improvements and optimizations, CMOS device structures and process steps remain to be rather conventional down to 1.2 µm, and real innovation or evolution is expected to come below 1.0 µm or in the sub-micron region.
S. Kohyama, J. Matsunaga, K. Hashimoto
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This paper describes current status and future prospect of CMOS technology for VLSI circuit applications. Though requiring various improvements and optimizations, CMOS device structures and process steps remain to be rather conventional down to 1.2 µm, and real innovation or evolution is expected to come below 1.0 µm or in the sub-micron region.
S. Kohyama, J. Matsunaga, K. Hashimoto
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International Electron Devices Meeting, 2019
A leading edge 5nm CMOS platform technology has been defined and optimized for mobile and HPC applications. This industry-leading 5nm technology features, for the first time, full-fledged EUV, and high mobility channel (HMC) finFETs with densest 0.021µm2
G. Yeap +58 more
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A leading edge 5nm CMOS platform technology has been defined and optimized for mobile and HPC applications. This industry-leading 5nm technology features, for the first time, full-fledged EUV, and high mobility channel (HMC) finFETs with densest 0.021µm2
G. Yeap +58 more
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Magnetotransistor in CMOS technology
IEEE Transactions on Electron Devices, 1986An investigation of the magnetic-field sensitivity of a lateral double-base contact n-p-n magnetotransistor compatible with CMOS technology is reported. An approximate theoretical analysis of the sensitivity is made. Two physical mechanisms are considered: current deflection and injection modulation. The deflection mechanism is more significant.
R.S. Popovic, R. Widmer
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2004 Asia-Pacific Radio Science Conference, 2004. Proceedings., 2005
RF CMOS characteristics have been traditionally regarded as poorer than those of Si-bipolar and compound devices. However, recent aggressive downsizing of CMOS devices has improved their RF characteristics significantly and some of them have already exceeded some Si-bipolar and GaAs transistors.
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RF CMOS characteristics have been traditionally regarded as poorer than those of Si-bipolar and compound devices. However, recent aggressive downsizing of CMOS devices has improved their RF characteristics significantly and some of them have already exceeded some Si-bipolar and GaAs transistors.
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2011
In this chapter, we will first simulate a very simple 3D device. A long channel n-type MOSFET (NMOS) is the simplest 3D simulation case for unipolar devices, as it is merely an extension of a 2D simulation. There is no variation along the z direction so only two planes are needed to perform a 3D simulation.
Simon Li, Yue Fu
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In this chapter, we will first simulate a very simple 3D device. A long channel n-type MOSFET (NMOS) is the simplest 3D simulation case for unipolar devices, as it is merely an extension of a 2D simulation. There is no variation along the z direction so only two planes are needed to perform a 3D simulation.
Simon Li, Yue Fu
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1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1981
This paper will report on a bulk CMOS technology based on HMOS, affording such features as high resistivity P substrate diffused wells and 2μm channel length N and P channel devices. A 4K static RAM test vehicle using this approach has demonstrated 25ns access time and microwatt standby power.
K. Yu +4 more
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This paper will report on a bulk CMOS technology based on HMOS, affording such features as high resistivity P substrate diffused wells and 2μm channel length N and P channel devices. A 4K static RAM test vehicle using this approach has demonstrated 25ns access time and microwatt standby power.
K. Yu +4 more
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2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846), 2005
Previously, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology ...
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Previously, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology ...
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1991
Complementary MOS (CMOS) is, by far, the technology of choice for the realization of integrated circuits on SOI substrates. This Chapter will compare CMOS processing on bulk silicon and on SOI wafers. Processing of both thin and thicker SOI films will be discussed.
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Complementary MOS (CMOS) is, by far, the technology of choice for the realization of integrated circuits on SOI substrates. This Chapter will compare CMOS processing on bulk silicon and on SOI wafers. Processing of both thin and thicker SOI films will be discussed.
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2004
In the 1940s the electronic history was marked by the invention of the transistor and only a decade after the first Integrated Circuit (IC) was realized. Nowadays, few decades after that invention, the CMOS Technology Platform is putting us in front of another major forefront: the capability to realize an entire system on a single piece of silicon, the
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In the 1940s the electronic history was marked by the invention of the transistor and only a decade after the first Integrated Circuit (IC) was realized. Nowadays, few decades after that invention, the CMOS Technology Platform is putting us in front of another major forefront: the capability to realize an entire system on a single piece of silicon, the
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Sensors and Actuators A: Physical, 1993
Abstract Sensor design and fabrication using industrial IC technologies has the advantages of batch fabrication and on-chip interface circuitry. Sensors made by CMOS or bipolar IC technology have been demonstrated for magnetic, temperature and radiation measurands.
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Abstract Sensor design and fabrication using industrial IC technologies has the advantages of batch fabrication and on-chip interface circuitry. Sensors made by CMOS or bipolar IC technology have been demonstrated for magnetic, temperature and radiation measurands.
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