Results 231 to 240 of about 7,631,832 (303)
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A perspective on CMOS technology trends
Proceedings of the IEEE, 1986Integrated circuit technology continues to evolve at a rapid pace, driven by the requirements of new applications for electronics of higher performance at ever lower cost. The attributes of CMOS technology in a ULSI environment are an ideal match to these requirements; thus CMOS is becoming the ubiquitous integrated circuit technology. The main feature
William C. Holton, Ralph K. Cavin III
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IBM Journal of Research and Development, 2000
The performance of integrated circuits has been improving exponentially for more than thirty years. During the next decade, the industry must overcome several technological challenges to sustain this remarkable pace of improvement. Challenges in lithography, transistor scaling, interconnections, circuit families, computer memory, and circuit design are
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The performance of integrated circuits has been improving exponentially for more than thirty years. During the next decade, the industry must overcome several technological challenges to sustain this remarkable pace of improvement. Challenges in lithography, transistor scaling, interconnections, circuit families, computer memory, and circuit design are
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Experimental Astronomy, 2006
An entry level overview of state-of-the-art CMOS detector technology is presented. Operating principles and system architecture are explained in comparison to the well-established CCD technology, followed by a discussion of important benefits of modern CMOS-based detector arrays.
Alan Hoffman +2 more
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An entry level overview of state-of-the-art CMOS detector technology is presented. Operating principles and system architecture are explained in comparison to the well-established CCD technology, followed by a discussion of important benefits of modern CMOS-based detector arrays.
Alan Hoffman +2 more
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Variability in nanoscale CMOS technology
Science China Information Sciences, 2011Moore’s Law technology scaling has improved VLSI performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore’s Law, a variety of challenges will need to be overcome. One of these challenges is management of process variation.
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1998 IEEE International Reliability Physics Symposium Proceedings 36th Annual (Cat No 98CH36173) RELPHY-98, 1998
This paper is a review of the latchup phenomena in past and present CMOS technologies. Both static and transient characterization techniques are described, as well as process related solutions and layout ground rule constraints. Technology scaling implications are discussed in the context of latchup holding voltage/current and minimum N/sup +/ to P/sup
M.J. Hargrove +5 more
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This paper is a review of the latchup phenomena in past and present CMOS technologies. Both static and transient characterization techniques are described, as well as process related solutions and layout ground rule constraints. Technology scaling implications are discussed in the context of latchup holding voltage/current and minimum N/sup +/ to P/sup
M.J. Hargrove +5 more
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Future of nano CMOS technology
2014 IEEE International Conference on Electron Devices and Solid-State Circuits, 2007Although silicon-based CMOS devices have dominated the integrated circuit applications over the past few decades, it is expected that the development of CMOS would reach its limits after the next decade because of the difficulties in downsizing and also some fundamental limits of MOSFETs.
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2014 IEEE International Electron Devices Meeting, 2014
We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs.
C. Lin +98 more
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We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs.
C. Lin +98 more
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Optical Fiber Communications Conference and Exhibition, 2020
GLOBALFOUNDRIES' monolithic 45nm CMOS-Silicon Photonics 300mm high-volume manufacturing platform based on 45nm RF technology node, and optimized for high performance and low power short-reach optical interconnects for on-chip and chip-to-chip ...
M. Rakowski +21 more
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GLOBALFOUNDRIES' monolithic 45nm CMOS-Silicon Photonics 300mm high-volume manufacturing platform based on 45nm RF technology node, and optimized for high performance and low power short-reach optical interconnects for on-chip and chip-to-chip ...
M. Rakowski +21 more
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Technology Options for Beyond-CMOS
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017CMOS integrated circuit technology for computation is at an inflexion point. Although this is the technology which has enabled the semiconductor industry to make vast progress over the past 30-plus years, it is expected to see challenges going beyond the ten year horizon, particularly from an energy efficiency point of view.
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Generalised CMOS---a technology independent CMOS IC design style
Proceedings of the 22nd ACM/IEEE conference on Design automation - DAC '85, 1985A CMOS IC design methodology is presented which allows a single design representation, captured at the symbolic level, to be implemented in different classes of CMOS fabrication technologies such as N-well, P-well, twin-well, and SOI. Extensive use is made of CAD tools to achieve automatic conversion from the technology-independent representation into ...
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