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Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems, 2007
Packet classification is central to modern network functionality, yet satisfactory memory usage and performance remains elusive at the highest speeds. The recent emergence of low-cost, highly parallel architectures provides a promising platform on which to realize increased classification performance.
Randy Smith, Dan Gibson, Shijin Kong
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Packet classification is central to modern network functionality, yet satisfactory memory usage and performance remains elusive at the highest speeds. The recent emergence of low-cost, highly parallel architectures provides a promising platform on which to realize increased classification performance.
Randy Smith, Dan Gibson, Shijin Kong
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IEEE Micro, 2000
The Hydra chip multiprocessor (CMP) integrates four MIPS-based processors and their primary caches on a single chip together with a shared secondary cache. A standard CMP offers implementation and performance advantages compared to wide-issue superscalar designs.
Lance Hammond +5 more
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The Hydra chip multiprocessor (CMP) integrates four MIPS-based processors and their primary caches on a single chip together with a shared secondary cache. A standard CMP offers implementation and performance advantages compared to wide-issue superscalar designs.
Lance Hammond +5 more
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The Compatibility of Copper CMP Slurries with CMP Requirements
Journal of The Electrochemical Society, 2003Cu is currently used as a replacement for aluminum in IC interconnections. One of the challenges of integrated circuit (IC) interconnection technology is the planarization process that involves fine copper lines patterning; the most perspective technique for Cu lines patterning is chemical mechanical planarization (CMP).
Y. Ein-Eli +3 more
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ACM SIGARCH Computer Architecture News, 2009
The fast simulation of chip multiprocessors (CMPs) presents a critical challenge to the architecture research community as both industry and academia shift their research focus to multicore design. Parallel simulation is a technique to accelerate microarchitecture simulation of CMPs by exploiting the inherent parallelism of CMPs.
Jianwei Chen +2 more
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The fast simulation of chip multiprocessors (CMPs) presents a critical challenge to the architecture research community as both industry and academia shift their research focus to multicore design. Parallel simulation is a technique to accelerate microarchitecture simulation of CMPs by exploiting the inherent parallelism of CMPs.
Jianwei Chen +2 more
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Application of a CMP Model to Tungsten CMP
Journal of The Electrochemical Society, 2001A general model of chemical mechanical polishing (CMP) has been derived which shows the dependence of the polishing rate on the concentration of chemicals and abrasives in the slurry. This paper applies the model to tungsten CMP and describes the chemistry of tungsten CMP in some detail.
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Fabrication of MWNT@CMPs and carbonized MWNT@CMPs for supercapacitors
Materials Chemistry and Physics, 2019Abstract Conjugated mesoporous/microporous polymers (CMPs) were incorporated onto the surfaces of multiwall carbon nanotubes (MWNT) to form MWNT@CMPs. The morphologies of MWNT@CMP composites varied with the adjustment of starting monomers for the preparation of polymers.
Hua Wang +4 more
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Proceedings of the 15th international symposium on System Synthesis - ISSS '02, 2002
This paper briefly sketches the current issues of chip multiprocessor (CMP) design for system LSI chip from the viewpoint of computer architects.
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This paper briefly sketches the current issues of chip multiprocessor (CMP) design for system LSI chip from the viewpoint of computer architects.
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Evaluating CMPs and Their Memory Architecture
2009Many-core processor architectures require scalable solutions that reflect the locality and power constraints of future generations of technology. This paper presents a CMP architecture that supports automatic mapping and dynamic scheduling of threads leaving the binary code devoid of any explicit communication. The thrust of this approach is to produce
Jesshope, C., Lankamp, M., Zhang, L.
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