Results 171 to 180 of about 1,113 (217)
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Design of explicit-pulse generators with CNTFET

2015 IEEE 11th International Conference on ASIC (ASICON), 2015
A novel single-edge pulse generator (S-PG) and a dual-edge pulse generator (D-PG) are designed with Carbon Nanotube Field Effect Transistor (CNTFET). In order to generate pulse signal alternately, the output is controlled by delayed clock signal. The single-edge pulse generator without pseudo PMOS can reduce power consumption.
Wang Qian, Wang Pengjun, Gong Daohui
openaire   +1 more source

Performance study of 12-CNTFET and GDI CNTFET based full adder in HSPICE

2014 International Conference on Advances in Engineering & Technology Research (ICAETR - 2014), 2014
This manuscript reports and analyzes 12-CNTFET and GDI CNTFET based full adder implementation at 32 nm level. As figures of merit, stability, power dissipation and Power Delay Product (PDP) are considered for the best overall performance. Intensive HSPICE simulations have been performed to investigate the distribution of the power and delay of the ...
null Habib Muhammad Nazir Ahmad   +4 more
openaire   +1 more source

Modelling a CNTFET with Undeposited CNT Defects

2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
The Carbon NanoTube Field Effect Transistor (CNTFET) is a promising device to supersede the MOSFET at the end of the technology roadmap of CMOS. When designing and manufacturing a CNTFET, additional features such as pitch, number and position of the CNTs must be considered to assess its performance.
Geunho Cho   +2 more
openaire   +1 more source

A Compact Noise Model for C-CNTFETs

ECS Journal of Solid State Science and Technology, 2017
In this paper we present a compact noise model for C-CNTFETs implemented in Verilog-A. After a brief description of the main noise sources existing in CNTFETs, which constitute a significant limitation in the design of analogue and logic CNTFETs circuits, we enhance a model, already proposed by us, considering the noise sources.
Marani R, Gelao G, Perri AG
openaire   +2 more sources

Contact resistance extraction methods for CNTFETs

2015 45th European Solid State Device Research Conference (ESSDERC), 2015
Three different methods for the extraction of the contact resistance based on both the well-known transfer length method (TLM) and two variants of the Y-function method have been applied to simulation and experimental data of CNTFETs and the results have been compared.
Anibal Pacheco-Sanchez   +3 more
openaire   +1 more source

Accurate SPICE compatible CNT interconnect and CNTFET models for circuit design and simulation

open access: yesMathematical and Computer Modelling, 2013
SPICE compatible CNT interconnect and CNTFET models in Verilog-A hardware description language are presented in this paper. Metallic CNTs are shown to have current saturation characteristics above a threshold voltage and then modelled with piecewise ...
Serhan Yamacli, Mutlu Avci
exaly   +2 more sources

Basics of CNTFET and Ternary Logic

2020
In this chapter, we present key aspects of the CNTFET technology. As indicated earlier, carbon nanotubes have bandgaps that are dependent on the diameter of the tubes [1]. Also, the bandgap turns out to be a measure of the threshold voltage of the CNTFET.
K. Sridharan   +2 more
openaire   +1 more source

A Review on MOSFET-Like CNTFETs

Science & Technology Journal, 2016
Carbon Nanotube Field Effect Transistor (CNTFET) is one of the promising devices for future nanoscale technologies. In this paper, we have studied the drain characteristics of MOSFET-like CNTFETs for different device parameters like, channel length, diameter of CNT, and number of tubes.
Vikash Prasad, Debaprasad Das
openaire   +1 more source

CNTFET-Based Memory Design

2020
As the feature size of device has been scaling down for many decades, conventional CMOS technology-based static random access memory (SRAM) has reached its limit due to significant leakage power. Therefore, carbon nanotube field effect transistor (CNTFET) can be considered most suitable alternative for SRAM.
Shashi Bala, Mamta Khosla, Raj Kumar
openaire   +1 more source

Memristor-CNTFET based Ternary Full Adders

2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), 2020
Recently multilevel systems are one of the hottest topics in the digital electronics field. Multi-level logic (MVL) overcomes the issues of interconnections. The ternary system is a promising system where the implementation complexity is low and more information can be stored compared to the binary logic system.
Amr Mohammaden   +3 more
openaire   +1 more source

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