Results 201 to 210 of about 4,664 (251)

SegMan-based dual-prior network with boundary-augmented hybrid attention for robust skin lesion segmentation. [PDF]

PLoS One
Wang J, Zhang T, Li P.
europepmc   +1 more source

Multi-Modal Anomaly Detection in Review Texts with Sensor-Derived Metadata Using Instruction-Tuned Transformers. [PDF]

Sensors (Basel)
Alhawiti KM.
europepmc   +1 more source

Automated, physics-guided AI framework for asymmetry-aware ferroelectric compact models. [PDF]

Sci Rep
Kim J, Lee J, Park J, Kim M, Kim H, Kang J, Cho H, Choi HW, Jeon J.   +8 more
europepmc   +1 more source

Benchmarking quantum kernels and modern vision models for compound facial expression recognition. [PDF]

Sci Rep
Florestiyanto MY, Surjono HD, Jati H.
europepmc   +1 more source

Resilient and verifiable outsourced attribute-based non-interactive oblivious transfer protocol for tactical edge networks. [PDF]

Sci Rep
Liu W, Fu B, Wang L.
europepmc   +1 more source

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Compute Unified Device Architecture Application Suitability

Computing in Science and Engineering, 2009
Graphics processing units (GPUs) can provide excellent speedups on some, but not all, general-purpose workloads. Using a set of computational GPU kernels as examples, the authors show how to adapt kernels to utilize the architectural features of a GeForce 8800 GPU and what finally limits the achievable performance.
Wen-Mei Hwu
exaly   +2 more sources

An Accelerated MJPEG 2000 Encoder Using Compute Unified Device Architecture

Communications in Computer and Information Science, 2010
With the recent tremendous increase in Graphics Processing Unit’s computing capability, using it as a co-processor of the CPU has become fundamental for achieving high overall throughput. Nvidia’s Compute Device Unified Architecture (CUDA) can greatly benefit single instruction multiple thread styled, computationally expensive programs. Video encoding,
Rajdeep Niyogi, Niyogi Rajdeep
exaly   +2 more sources

Variable block size motion estimation implementation on compute unified device architecture (CUDA)

2013 IEEE International Conference on Consumer Electronics (ICCE), 2013
This paper proposes a highly parallel variable block size full search motion estimation algorithm with concurrent parallel reduction (CPR) on graphics processing unit (GPU) using compute unified device architecture (CUDA). This approach minimizes memory access latency by using high-speed on-chip memory of GPU.
Dong-Kyu Lee, Seoung-Jun Oh
exaly   +2 more sources

Implementation of a Lattice Boltzmann kernel using the Compute Unified Device Architecture developed by nVIDIA

Computing and Visualization in Science, 2008
In this article a very efficient implementation of a 2D-Lattice Boltzmann kernel using the Compute Unified Device Architecture (CUDA™) interface developed by nVIDIA® is presented. By exploiting the explicit parallelism exposed in the graphics hardware we obtain more than one order in performance gain compared to standard CPUs.
Jonas Tolke
exaly   +2 more sources