Results 11 to 20 of about 62,688 (226)
Design and Analysis of On-Chip CPU Pipelined Caches [PDF]
, 2000 The access time of the first level on-chip cache usually imposes the cycle time of high-performance VLSI processors. The only way to reduce the effect of cache access time on processor cycle time is the use of pipelined caches. A timing model for on-chip caches has recently been presented in [1].
C. Ninos, H. T. Vergos, D. Nikolos
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Iterative cache simulation of embedded CPUs with trace stripping [PDF]
Proceedings of the seventh international workshop on Hardware/software codesign - CODES '99, 1999 Trace-driven cache simulation is a time-consuming yet valuable procedure for evaluating the performance of embedded memory systems. In this paper we present a novel technique, called iterative cache simulation, to produce a variety of performance metrics for several different cache configurations. Compared with previous work in this field, our approach
Z. Wu, W. Wolf
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Method of Timing Attack for Linux Against KASLR [PDF]
Jisuanji gongcheng, 2021 For Linux systems with Kernel Address Space Layout Randomization(KASLR) protection, this paper proposes a Cache instant attack method based on CPU prefetch instruction.
CONG Mou, ZHANG Ping, WANG NING
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CASY: A CPU Cache Allocation System for FaaS Platform
2022 22nd IEEE International Symposium on Cluster, Cloud and Internet Computing (CCGrid), 2022 Armel Jeatsa +2 more
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Design of Cache Memory System for Next Generation CPU
IEMEK Journal of Embedded Systems and Applications, 2016 Ok-Rae Jo, Jung-Hoon Lee
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Hierarchical cache configuration based on hybrid SOT- and STT-MRAM
AIP Advances, 2023 With the rapid growth of big data information and the continuous iteration progress of CPU architecture, the implementation of a new memory-based cache architecture is urgent and challenging. In the paper, a CPU cache architecture system based on MRAM is
Shaopu Han, Qiguang Wang, Yanfeng Jiang
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JackHammer: Efficient Rowhammer on Heterogeneous FPGA-CPU Platforms
Transactions on Cryptographic Hardware and Embedded Systems, 2020 After years of development, FPGAs are finally making an appearance on multi-tenant cloud servers. Heterogeneous FPGA-CPU microarchitectures require reassessment of common assumptions about isolation and security boundaries, as they introduce new attack ...
Zane Weissman +5 more
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IET Communications, EarlyView., 2022 Abstract The goal of this work is to investigate how the self‐awareness characteristic of autonomic computing, paired with existing performance optimization rules, may be used in applications to minimise multi‐core processor performance concerns. The suggested self‐awareness technique can assist applications in self‐execution while also assisting other
Surendra Kumar Shukla +8 more
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High-Performance and Flexible Design Scheme with ECC Protection in the Cache
Micromachines, 2022 To improve the reliability of static random access memory (SRAM), error-correcting codes (ECC) are typically used to protect SRAM in the cache. While improving the reliability, we also need additional circuits to support ECC, including encoding and ...
Yulun Zhou +3 more
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Precision planter monitoring system based on mobile communication network
IET Networks, EarlyView., 2022 Abstract Sowing is an important link in agricultural production and the basis for ensuring high yields and bumper harvests. Agriculture requires precision plows with good performance and stable work. However, the seeding process is in a completely closed state, and the operator relies mainly on experience to judge the operating state and performance of
Bing Li, Jiyun Li
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