Results 11 to 20 of about 62,963 (220)
Design of Cache Memory System for Next Generation CPU
IEMEK Journal of Embedded Systems and Applications, 2016 Ok-Rae Jo, Jung-Hoon Lee
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Cache-optimized BFS on multi-core CPUs [PDF]
Proceedings of the 1st FastCode Programming ChallengeSalvatore Domenico Andaloro +2 more
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Data Rate Estimation for Wireless Core-to-Cache Communication in Multicore CPUs
Моделирование и анализ информационных систем, 2015 In this paper, a principal architecture of common purpose CPU and its main components are discussed, CPUs evolution is considered and drawbacks that prevent future CPU development are mentioned.
Maria S. Komar +4 more
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Method of Timing Attack for Linux Against KASLR [PDF]
Jisuanji gongcheng, 2021 For Linux systems with Kernel Address Space Layout Randomization(KASLR) protection, this paper proposes a Cache instant attack method based on CPU prefetch instruction.
CONG Mou, ZHANG Ping, WANG NING
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Hierarchical cache configuration based on hybrid SOT- and STT-MRAM
AIP Advances, 2023 With the rapid growth of big data information and the continuous iteration progress of CPU architecture, the implementation of a new memory-based cache architecture is urgent and challenging. In the paper, a CPU cache architecture system based on MRAM is
Shaopu Han, Qiguang Wang, Yanfeng Jiang
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Evaluating associativity in CPU caches [PDF]
IEEE Transactions on Computers, 1989 The authors present new and efficient algorithms for simulating alternative direct-mapped and set-associative caches and use them to quantify the effect of limited associativity on the cache miss ratio. They introduce an algorithm, forest simulation, for simulating alternative direct-mapped caches and generalize one, which they call all-associativity ...
M.D. Hill, A.J. Smith
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IET Communications, EarlyView., 2022 Abstract The goal of this work is to investigate how the self‐awareness characteristic of autonomic computing, paired with existing performance optimization rules, may be used in applications to minimise multi‐core processor performance concerns. The suggested self‐awareness technique can assist applications in self‐execution while also assisting other
Surendra Kumar Shukla +8 more
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JackHammer: Efficient Rowhammer on Heterogeneous FPGA-CPU Platforms
Transactions on Cryptographic Hardware and Embedded Systems, 2020 After years of development, FPGAs are finally making an appearance on multi-tenant cloud servers. Heterogeneous FPGA-CPU microarchitectures require reassessment of common assumptions about isolation and security boundaries, as they introduce new attack ...
Zane Weissman +5 more
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Precision planter monitoring system based on mobile communication network
IET Networks, EarlyView., 2022 Abstract Sowing is an important link in agricultural production and the basis for ensuring high yields and bumper harvests. Agriculture requires precision plows with good performance and stable work. However, the seeding process is in a completely closed state, and the operator relies mainly on experience to judge the operating state and performance of
Bing Li, Jiyun Li
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High-Performance and Flexible Design Scheme with ECC Protection in the Cache
Micromachines, 2022 To improve the reliability of static random access memory (SRAM), error-correcting codes (ECC) are typically used to protect SRAM in the cache. While improving the reliability, we also need additional circuits to support ECC, including encoding and ...
Yulun Zhou +3 more
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