Results 21 to 30 of about 62,688 (226)
Super-Scalar RAM-CPU Cache Compression [PDF]
22nd International Conference on Data Engineering (ICDE'06), 2006 High-performance data-intensive query processing tasks like OLAP, data mining or scientific data analysis can be severely I/O bound, even when high-end RAID storage systems are used. Compression can alleviate this bottleneck only if encoding and decoding speeds significantly exceed RAID I/O bandwidth.
M. Zukowski, S. Heman, N. Nes, P. Boncz
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Large-capacity and high-speed instruction cache based on divide-by-2 memory banks
Journal of Electronic Science and Technology, 2021 An increase in the cache capacity is usually accompanied by a decrease in access speed. To balance the capacity and performance of caches, this paper proposes an instruction cache (ICache) architecture based on divide-by-2 memory banks (D2MB-ICache). The
Qing-Qing Li +4 more
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A Conversation History-Based Q&A Cache Mechanism for Multi-Layered Chatbot Services
Applied Sciences, 2021 Chatbot technologies have made our lives easier. To create a chatbot with high intelligence, a significant amount of knowledge processing is required. However, this can slow down the reaction time; hence, a mechanism to enable a quick response is needed.
Ozoda Makhkamova, Doohyun Kim
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Real-Time Detection for Cache Side Channel Attack using Performance Counter Monitor
Applied Sciences, 2020 Cache side channel attacks extract secret information by monitoring the cache behavior of a victim. Normally, this attack targets an L3 cache, which is shared between a spy and a victim.
Jonghyeon Cho +5 more
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A Real-Time Cache Side-Channel Attack Detection System on RISC-V Out-of-Order Processor
IEEE Access, 2021 Computer designers have included techniques such as speculative execution and caching to optimize speed and performance. Unfortunately, they could be exploited by the recently discovered cache-side channel attack, spectre. The purpose of this research is
Anh-Tien Le +5 more
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Reuse Cache for Heterogeneous CPU-GPU Systems
, 2021 It is generally observed that the fraction of live lines in shared last-level caches (SLLC) is very small for chip multiprocessors (CMPs). This can be tackled using promotion-based replacement policies like re-reference interval prediction (RRIP) instead of LRU, dead-block predictors, or reuse-based cache allocation schemes. In GPU systems, similar LLC
Shah, Tejas +3 more
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Accelerator Memory Reuse in the Dark Silicon Era [PDF]
, 2014 Accelerators integrated on-die with General-Purpose CPUs (GP-CPUs) can yield significant performance and power improvements. Their extensive use, however, is ultimately limited by their area overhead; due to their high degree of specialization, the ...
Carloni, L.P. +4 more
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Improving Performance Isolation on Chip Multiprocessors via an Operating System Scheduler [PDF]
, 2012 We describe a new operating system scheduling algorithm that improves performance isolation on chip multiprocessors (CMP). Poor performance isolation occurs when an application’s performance is determined by the behaviour of its co-runners, i.e., other ...
Federova, Alexandra +2 more
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MARACAS: a real-time multicore VCPU scheduling framework [PDF]
, 2016 This paper describes a multicore scheduling and load-balancing framework called MARACAS, to address shared cache and memory bus contention. It builds upon prior work centered around the concept of virtual CPU (VCPU) scheduling.
Cheng, Zhuoqun +3 more
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IOb-Cache: A High-Performance Configurable Open-Source Cache
Algorithms, 2021 Open-source processors are increasingly being adopted by the industry, which requires all sorts of open-source implementations of peripherals and other system-on-chip modules.
João V. Roque +3 more
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