Results 31 to 40 of about 62,963 (220)

ESL: A High-Performance Skiplist with Express Lane

open access: yesApplied Sciences, 2023
With the increasing capacity and cost-efficiency of DRAM in multi-core environments, in-memory databases have emerged as fundamental solutions for delivering high performance.
Yedam Na   +4 more
doaj   +1 more source

Locating Cache Performance Bottlenecks Using Data Profiling [PDF]

open access: yes, 2010
Effective use of CPU data caches is critical to good performance, but poor cache use patterns are often hard to spot using existing execution profiling tools. Typical profilers attribute costs to specific code locations.
Morris, Robert Tappan   +2 more
core   +3 more sources

CacheOut: Leaking Data on Intel CPUs via Cache Evictions [PDF]

open access: yes2021 IEEE Symposium on Security and Privacy (SP), 2021
Recent transient-execution attacks, such as RIDL, Fallout, and ZombieLoad, demonstrated that attackers can leak information while it transits through microarchitectural buffers. Named Microarchitectural Data Sampling (MDS) by Intel, these attacks are likened to "drinking from the firehose", as the attacker has little control over what data is observed ...
van Schaik, Stephan   +4 more
openaire   +2 more sources

Data Rates Assessment on L2–L3 CPU Bus and Bus between CPU and RAM in Modern CPUs

open access: yesМоделирование и анализ информационных систем, 2017
In this paper, a modern CPU architecture with several different cache levels is described, and current CPU performance limitations such as silicone physical limitations or frequency increase bounds are mentioned.
Maria S. Komar
doaj   +1 more source

Evaluating Cache Coherent Shared Virtual Memory for Heterogeneous Multicore Chips [PDF]

open access: yes, 2013
The trend in industry is towards heterogeneous multicore processors (HMCs), including chips with CPUs and massively-threaded throughput-oriented processors (MTTOPs) such as GPUs.
Hechtman, Blake A., Sorin, Daniel J.
core   +2 more sources

SIMULADOR DE UCP COM SUPORTE À MEMÓRIA CACHE E PIPELINE

open access: yesColloquium Exactarum, 2014
A common problem in computer architecture disciplines is the real dynamics of the processes occurring internally in hardware. The working of a CPU, for example, is complex and its understanding is fundamental to the use of their resources.
Artur Jordão Lima Correia   +4 more
doaj   +1 more source

Cache Misses and the Recovery of the Full AES 256 Key

open access: yesApplied Sciences, 2019
The CPU cache is a hardware element that leaks significant information about the software running on the CPU. Particularly, any application performing sequences of memory access that depend on sensitive information, such as private keys, is susceptible ...
Samira Briongos   +3 more
doaj   +1 more source

A Survey of Cache Bypassing Techniques

open access: yesJournal of Low Power Electronics and Applications, 2016
With increasing core-count, the cache demand of modern processors has also increased. However, due to strict area/power budgets and presence of poor data-locality workloads, blindly scaling cache capacity is both infeasible and ineffective.
Sparsh Mittal
doaj   +1 more source

Analyzing Data Locality on GPU Caches Using Static Profiling of Workloads

open access: yesIEEE Access, 2023
The diversity of workloads drives studies to use GPU more effectively to overcome the limited memory of GPUs. Precisely, it is essential to understand and utilize data locality of workloads to utilize the memory and cache efficiently, which is relatively
Jieun Kim, Hyeonsang Eom, Yoonhee Kim
doaj   +1 more source

Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM

open access: yesIEEE Access, 2020
Packet processing performance of Network Function Virtualization (NFV)-aware environment depends on the memory access performance of commercial-off-the-shelf (COTS) hardware systems.
Tomohiro Korikawa   +3 more
doaj   +1 more source

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