Results 31 to 40 of about 62,688 (226)

Locating Cache Performance Bottlenecks Using Data Profiling [PDF]

, 2010
Effective use of CPU data caches is critical to good performance, but poor cache use patterns are often hard to spot using existing execution profiling tools. Typical profilers attribute costs to specific code locations.
Morris, Robert Tappan, Pesterev, Aleksey, Zeldovich, Nickolai   +2 more
core   +3 more sources

ESL: A High-Performance Skiplist with Express Lane

Applied Sciences, 2023
With the increasing capacity and cost-efficiency of DRAM in multi-core environments, in-memory databases have emerged as fundamental solutions for delivering high performance.
Yedam Na, Bonmoo Koo, Taeyoon Park, Jonghyeok Park, Wook-Hee Kim   +4 more
doaj   +1 more source

HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems [PDF]

, 1968
Spin-Transfer Torque RAM (STT-RAM) is widely considered a promising alternative to SRAM in the memory hierarchy due to STT-RAM's non-volatility, low leakage power, high density, and fast read speed.
Adegbija, Tosiron, Kuan, Kyle
core   +4 more sources

Measuring Data Access Latency in Large CPU Caches

Proceedings of the International Symposium on Memory Systems
Shaotong Sun, Yifan Zhu, Xingzhi Ye, Chen Ding   +3 more
openaire   +2 more sources

Evaluating Cache Coherent Shared Virtual Memory for Heterogeneous Multicore Chips [PDF]

, 2013
The trend in industry is towards heterogeneous multicore processors (HMCs), including chips with CPUs and massively-threaded throughput-oriented processors (MTTOPs) such as GPUs.
Hechtman, Blake A., Sorin, Daniel J.
core   +2 more sources

Data Rates Assessment on L2–L3 CPU Bus and Bus between CPU and RAM in Modern CPUs

Моделирование и анализ информационных систем, 2017
In this paper, a modern CPU architecture with several different cache levels is described, and current CPU performance limitations such as silicone physical limitations or frequency increase bounds are mentioned.
Maria S. Komar
doaj   +1 more source

SIMULADOR DE UCP COM SUPORTE À MEMÓRIA CACHE E PIPELINE

Colloquium Exactarum, 2014
A common problem in computer architecture disciplines is the real dynamics of the processes occurring internally in hardware. The working of a CPU, for example, is complex and its understanding is fundamental to the use of their resources.
Artur Jordão Lima Correia, Mario Augusto Pazoti, Francisco Assis da Silva, Leandro Luiz de Almeida, Danillo Roberto Pereira   +4 more
doaj   +1 more source

Cache Misses and the Recovery of the Full AES 256 Key

Applied Sciences, 2019
The CPU cache is a hardware element that leaks significant information about the software running on the CPU. Particularly, any application performing sequences of memory access that depend on sensitive information, such as private keys, is susceptible ...
Samira Briongos, Pedro Malagón, Juan-Mariano de Goyeneche, Jose M. Moya   +3 more
doaj   +1 more source

A Survey of Cache Bypassing Techniques

Journal of Low Power Electronics and Applications, 2016
With increasing core-count, the cache demand of modern processors has also increased. However, due to strict area/power budgets and presence of poor data-locality workloads, blindly scaling cache capacity is both infeasible and ineffective.
Sparsh Mittal
doaj   +1 more source

Analyzing Data Locality on GPU Caches Using Static Profiling of Workloads

IEEE Access, 2023
The diversity of workloads drives studies to use GPU more effectively to overcome the limited memory of GPUs. Precisely, it is essential to understand and utilize data locality of workloads to utilize the memory and cache efficiently, which is relatively
Jieun Kim, Hyeonsang Eom, Yoonhee Kim
doaj   +1 more source