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Some transforms in cyclic redundancy check (CRC) computation
2011 International Conference on Electrical and Control Engineering, 2011Some transforms in cyclic redundancy check (CRC) computation, such as the multiplication of two messages' polynomials, shift, complement, and different initial (defaulted) remainder of a message, are studied. The relationships of the CRCs between the transformed message and the original one are also addressed from the mathematical point of view.
Aijun Wen
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2011 IEEE 19th Signal Processing and Communications Applications Conference (SIU), 2011
Cyclic Redundancy Checks (CRCs) are extensively used for effective error detection in communication systems. Previous studies evaluate the performance of CRC generator polynomials solely based on their Undetectable Error (UE) criterion without taking retransmission and overhead dynamics into account.
Huseyin Arslan
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Cyclic Redundancy Checks (CRCs) are extensively used for effective error detection in communication systems. Previous studies evaluate the performance of CRC generator polynomials solely based on their Undetectable Error (UE) criterion without taking retransmission and overhead dynamics into account.
Huseyin Arslan
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Realization of CRC (Cyclic Redundancy Check) Based on LabView
Applied Mechanics and Materials, 2014Algorithm and characteristics of CRC were investigated, and a pipeline algorithm steps to achieve it was introduced. The Modbus protocol RTU mode with CRC-16 was developed based on LabView using two methods, embedded c statements and graphical language based on LabView2012.
Tang Zhong
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CRC (Cyclic Redundancy Check) Implementation in High-Speed Semiconductor Memory
2015 8th International Conference on Control and Automation (CA), 2015This paper presents a CRC scheme for the semiconductor memory devices. Conventional error detecting method by using the ATM-8 HEC code leads to a considerable burden on the timing margin at the time of reading and writing of the low power memory devices for CRC(Cyclic Redundancy Check) calculations.
J. Lee
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Implementation of Table-Based Cyclic Redundancy Check (CRC-32) for Gigabit Ethernet Applications
2023 4th International Conference for Emerging Technology (INCET), 2023As the transaction data is Over 2.5 quintillion bytes per day. To transmit data between datacenters, Ethernet networks requires high speed and fast error detection techniques.
P Kishore
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2023 26th International Conference on Computer and Information Technology (ICCIT), 2023
QCA is considered as the replacement of CMOS technology for its attractive features that overcome the limitation of CMOS. Many designs of error detector circuits like parity checkers were proposed in QCA platform; but CRC circuit design in QCA platform ...
Mohammad Ishtiaque Khan +1 more
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QCA is considered as the replacement of CMOS technology for its attractive features that overcome the limitation of CMOS. Many designs of error detector circuits like parity checkers were proposed in QCA platform; but CRC circuit design in QCA platform ...
Mohammad Ishtiaque Khan +1 more
exaly +3 more sources
A self-timed cyclic redundancy check (CRC) in VLSI
Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg, 1999A self-timed approach to implement a cyclic redundancy check (CRC) for the application of telecommunications is described. The approach is oriented toward multiple channel communications. The paper presents a new scheme to handle an asynchronous feedback to implement the CRC engine.
S.Henry Li, Charles A. Zukowski
semanticscholar +3 more sources

