Results 171 to 180 of about 3,906 (206)

Interleaved cyclic redundancy check (CRC) code

The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003, 2004
In this paper, we investigate interleaved cyclic redundancy check (CRC) code. The interleaved CRC can be obtained by merging independent small message blocks into one large block (merged interleaving) or by dividing the original message block into independent small sub blocks (divided interleaving) and then by alternatively dividing the resulting ...
null Jun Jin Kong, K.K. Parhi
openaire   +2 more sources

A symbol based algorithm for hardware implementation of cyclic redundancy check (CRC)

Proceedings VHDL International Users' Forum. Fall Conference, 2002
Describes a symbolic simulation-based algorithm to derive optimized Boolean equations for a parameterizable data width CRC generator/checker. The equations are then used to implement a data flow representation of the CRC circuit in VHDL. The VHDL description is subsequently synthesized to gates.
R. Nair, G. Ryan, F. Farzaneh
openaire   +2 more sources

Pipelined Cyclic Redundancy Check (CRC) Calculation

2007 16th International Conference on Computer Communications and Networks, 2007
Traditional methods to calculate CRC suffer from diminishing returns. Doubling the data width doesn't double the maximum data throughput, the worst case timing path becomes slower. Feedback in the traditional implementation makes pipelining problematic. However, the on chip data width used for high throughput protocols is constantly increasing.
Mathys Walma
openaire   +2 more sources

Embedding a secondary communication channel transparently within a cyclic redundancy check (CRC)

IBM Journal of Research and Development, 2001
Techniques are proposed for transparently recapturing part of the capacity of a cyclic redundancy check (CRC) and using the recaptured capacity to carry a secondary communication channel. To do this, a transmitter induces CRC violations in outbound packets of a primary channel according to a set of error templates that are known to both the transmitter
D. R. Irvin
openaire   +2 more sources

The Use of Cyclic Redundancy Check (CRC-32) and Adler-32 Checksums for Source Code Verification

Drug Information Journal, 2003
The need for electronic files, specifically computer programs or source code, to be traceable is widely recognized. Certain types of checksums, a form of digital signature, provide a practical and efficient method of accomplishing that. This paper will show the rationale for using the Cyclic Redundancy Check (CRC-32) and Adler-32 checksums and present ...
A. Glaser
openaire   +2 more sources

Cyclic Redundancy Check (CRC)

, 2011
openaire   +2 more sources

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced [PDF]

IEEE Signal Processing Letters, 2014
Cyclic Redundancy Check (CRC) is often employed in data storage and communications to detect errors. The 3GPP-LTE wireless communication standard uses a 24-bit CRC with every turbo coded frame, thus, the CRC can be exploited to detect residual errors and
Carlo Condò, Maurizio Martina, Gianluca Piccinini   +2 more
exaly   +2 more sources

Construction of Cyclic Redundancy Check Codes for SDDC Decoding in DRAM Systems

IEEE Transactions on Circuits and Systems II: Express Briefs, 2023
Single device data correction (SDDC) is a main reliability, availability, and serviceability feature of DRAM systems in servers due to the significant hard-failure rate associated with DRAM devices.
Jiho Kim, Soonhee Kwon, Dong-Joon Shin   +2 more
exaly   +2 more sources

Performance of polar codes with low complexity cyclic redundancy check aided bit‐flipping for successive cancellation list decoding over power line channels

International Journal of Communication Systems, 2023
Power lines have complex transmission characteristics and noise interference when used as information transmission channel, thus limiting their data‐carrying rate and reliability.
Yu Zhou, Yue Li, Shuangshuang Zhao, Fan Gao, Chao Zhou, Zhuowen Mu   +5 more
semanticscholar   +1 more source

Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express® 6.0

IEEE Symposium on High-Performance Interconnects, 2023
PCI Express® (PCIe®) specification has been doubling the data rate every generation in a backward compatible manner every three years. PCIe 6.0 specification will adopt PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach, cost, and power ...
Debendra Das Sharma, Swadesh Choudhary
semanticscholar   +1 more source