Results 1 to 10 of about 83,045 (156)
IET Circuits, Devices and Systems, 2022 Mismatch in the binary‐weighted capacitive digital‐to‐analog converter (DAC) greatly affects the linearity of the successive‐approximation‐register (SAR) ADC by deteriorating the total harmonic distortion (THD).
Li Dong +8 more
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Asynchronous SAR ADC with self‐timed track‐and‐hold
Electronics Letters, 2023 This paper presents an asynchronous SAR ADC featuring a self‐timed track‐and‐hold (STH) architecture. The design aims to address the common timing issue of divider‐based clock generation, where the fixed‐time track‐and‐hold (FTH) period often results in ...
Sunghyun Bae +4 more
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A novel bandgap voltage reference based on folding compensation
Electronics Letters, 2023 This letter proposes a novel bandgap reference circuit that utilizes both curvature and folding compensation to achieve a temperature coefficient (TC) of 2.23 ppm/°C.
Mingyu Liu +4 more
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Method of high timing resolution pulse synthesis based on virtual sampling [PDF]
Metrology and Measurement Systems, 2022 Adjustable-width pulse signals are widely used in systems such as test equipment for hold time, response time and radar testing. In this study, we proposed a pulse generation method based on virtual sampling with ultra-high pulse width resolution. In the
Hanglin Liu +4 more
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A 1.2V −55°C‐125°C ultra‐low noise bandgap voltage reference without start‐up circuit
Electronics Letters, 2023 This paper proposes a novel bandgap voltage reference (BGR) with low temperature coefficient, ultra‐low noise and without start‐up circuit. Designed in a TSMC 180‐nm CMOS technology, this bandgap voltage reference operates in the temperature range of −55
Linzhi Tao, Haoyu Zhuang, Qiang Li
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A neural network based background calibration for pipelined‐SAR ADCs at low hardware cost
Electronics Letters, 2023 This paper proposes a background calibration scheme for the pipelined‐Successive Approximation Register (SAR) Analog‐to‐Digital Converter (ADC) based on the neural network.
Yuguo Xiang +5 more
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IET Optoelectronics, 2023 Optical digital‐to‐analog converters (DACs) are key to overcoming the enormous power consumption caused by the slowdown of Moore's Law. In previous work, an optical DAC consisting of a signal generator and an intensity converter was presented.
Yohei Aikawa, Hiroyuki Uenohara
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Electronics Letters, 2022 The authors present a low‐power area‐efficient subarray beamforming receiver (RX) structure for a miniaturized 3‐D ultrasound imaging system. Given that the delay‐and‐sum (DAS) and digitization functions consume most of the area and power in the receiver,
Seungah Lee, Soohyun Yun, Joonsung Bae
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A capacitor mismatch calibration scheme for SAR ADC based on genetic algorithm
Electronics Letters, 2023 Capacitor mismatch problem due to process variation causes weight error, which deteriorates the linearity of SAR ADC. In this paper, a novel calibration scheme based on genetic algorithm(GA) combined with a radix‐less‐than‐2 SAR ADC is proposed to ...
Yujia Huang +4 more
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Electronics Letters, 2023 This letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive‐approximation register (SAR) analogue‐to‐digital converter (ADC). The offset calibration technique is proposed to reduce the comparator offset mismatch that degrades the linearity of ...
Jaehyuk Lee +9 more
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