Results 141 to 150 of about 3,174 (179)

Low-Cost FPGA-Based Digital-to-Time Converter

Latin American Symposium on Circuits and Systems
In this paper, we present a Digital-to-Time Converter (DTC) based on a low-cost FPGA platform, utilizing the Vernier with oscillators architecture. A DTC is a circuit that converts digital information into a very accurate time output.
Vilmondes Ribeiro Silva, D. Colombo, Tomás Perpetuo Corrêa   +2 more
semanticscholar   +1 more source

Post-Layout Automated Optimization for Capacitor Array in Digital-to-Time Converter

Design, Automation and Test in Europe
The integral nonlinearity (INL) of Digital-to-Time Converter (DTC) in fractional-N phase-locked loops introduces fractional spurs, especially at near-integer channels, resulting in increased jitter.
Hefei Wang, Jianghao Su, Junhe Xue, Haoran Lyu, Junhua Zhang, Longyang Lin, Kai Chen, Lijuan Yang, Shenghua Zhou   +8 more
semanticscholar   +1 more source

A 1ps Resolution Two-Step Time-to-digital Converter Using Parallel Digital-to-time Converters

International Symposium on Next-Generation Electronics, 2021
A two-step time-to-digital converter (TDC) based on digital-to-time converter (DTC) is proposed in this paper. This architecture uses DTC as delay cell, it changes DTC’s delay time by adjusting the DTC’s delay control words(DCW) , and sets the ...
Yiheng Xi, Bo Wang, Minghim Lui, Chen Zhang, Cong Lin   +4 more
semanticscholar   +1 more source

A Small-footprint Power-efficient High-performance Digital-to-Time Converter with a Programmable Delay Chain-Based Segmentation

Proceedings of the 2nd International Symposium on Integrated Circuit Design and Integrated Systems
Digital-to-Time Converter (DTC) plays a key role in modern high-speed integrated circuits and systems, finding extensive applications in crucial scenarios concerning timing and latency, like high-speed SerDes (Serializer/Deserializer) interfaces, Phase ...
Wenchao Wang
semanticscholar   +1 more source

All-Digital Cost-Efficient CMOS Digital-to-Time Converter Using Binary-Weighted Pulse Expansion

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020
This brief presents a cost-efficient all-digital CMOS digital-to-time converter (DTC) that innovatively applies binary-weighted pulse expansion. The DTC consists of a pulse generator (PG) for pulse generation ( $t_{p}$ ), a binary-weighted pulse ...
Chun-Chi Chen, Chorng-Sii Hwang, Kai-Hsiang Chang   +2 more
semanticscholar   +1 more source

A 1.6-to-3.0-GHz Fractional- ${N}$ MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power

IEEE Journal of Solid-State Circuits, 2019
This article analyzes the jitter-power tradeoff in multiplying delay-locked loops (MDLLs), which differs from the more typical phase-locked loop one, and identifies a design optimization criterion.
Alessio Santiccioli, M. Mercandelli, A. Lacaita, C. Samori, S. Levantino   +4 more
semanticscholar   +2 more sources

A High-Linearity Digital-to-Time Converter Design for Fractional-N Sub-sampling PLL

International Conference on Information Communication and Management
In this paper, we propose a digital-to-time converter (DTC) design for Fractional-N Sub-sampling Phase-Locked Loop (SSPLL). The proposed design employs a parallel switching structure, re-timing technique, and complementary circuit to improve the ...
Jiangnan Li, Wangqing Wu, Ke Cao, Xinyi Zhang, Haigang Feng   +4 more
semanticscholar   +1 more source

A Self-Calibrated Digital-to-Time Converter with High-Resolution and Wide-Range Performance Using Multi-Level Tunable Delay Cells

China Semiconductor Technology International Conference
Digital-to-time converter (DTC) is widely used in automatic test equipment (ATE) and electronic measurement systems. However, high-resolution and wide-range DTCs usually require a large chip area.
Yanhui Zhao, Zhengrui Chen, Shizhang Wang, Cheng Zhuo, Li Zhang   +4 more
semanticscholar   +1 more source

Programmable Delay-Line with High-Resolution Time Steps Implemented in a Digital-to-Time Converter IP-Core for FPGAs and SoCs

Nuclear Science Symposium and Medical Imaging Conference, 2020
In this paper, we present an innovative Digital-to-Time Converter Programmable Delay Line (DTC-PDL) IP-Core to generate a delay with a high resolution for Xilinx Field-Programmable Gate Array (FPGA) and System-on-Chip (SoC) devices. Compared to solutions
N. Corna, N. Lusardi, F. Garzetti, S. Salgaro, K. Quinones, A. Geraci   +5 more
semanticscholar   +1 more source

A 0.05–1.5-GHz PVT-Insensitive Digital-to-Time Converter for QKD Applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
This work introduces a dual-channel digital-to-time converter (DTC) featuring a broad tuning range, which utilizes a dual delay-locked loop (DLL) architecture to achieve clock or data deskewing and precise timing adjustment effectively.
Haiyue Yan, Yan Ye, Wenjia Li, Xuefei Bai   +3 more
semanticscholar   +1 more source