Results 251 to 260 of about 77,045 (305)
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2015
One of the most challenging tasks in analog circuit design is to adapt a functional block to ever-new CMOS process technologies. For digital circuits, the number of gates per square milimeter approximately doubles per chip generation. Integration of analog parts in recent deep submicron technologies is much more difficult and additionally complicated ...
Basab Bijoy Purkayastha +1 more
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One of the most challenging tasks in analog circuit design is to adapt a functional block to ever-new CMOS process technologies. For digital circuits, the number of gates per square milimeter approximately doubles per chip generation. Integration of analog parts in recent deep submicron technologies is much more difficult and additionally complicated ...
Basab Bijoy Purkayastha +1 more
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2022
This thesis was scanned from the print manuscript for digital preservation and is copyright the author. Researchers can access this thesis by asking their local university, institution or public library to make a request on their behalf. Monash staff and postgraduate students can use the link in the References field.
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This thesis was scanned from the print manuscript for digital preservation and is copyright the author. Researchers can access this thesis by asking their local university, institution or public library to make a request on their behalf. Monash staff and postgraduate students can use the link in the References field.
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IETE Journal of Education, 2011
AbstractThe paper describes the phase locked loop (PLL) in detail. Emphasis is on Digital Phase Locked loops (DPLL) and All-Digital Phase Locked Loops (ADPLL). Important parameters of the PLLs are described. Different sub-blocks of DPLL and ADPLL are described and discussed in detail. An example design of ADPLL is also discussed.
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AbstractThe paper describes the phase locked loop (PLL) in detail. Emphasis is on Digital Phase Locked loops (DPLL) and All-Digital Phase Locked Loops (ADPLL). Important parameters of the PLLs are described. Different sub-blocks of DPLL and ADPLL are described and discussed in detail. An example design of ADPLL is also discussed.
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Synthesizable Digital Phase Locked Loop Implementation
Advanced Materials Research, 2013Phase locked loop (PLL) is a very common circuit in the most of the electrical devices. The systems where needed clock or data recovery or frequency synthesis, PLL is the most cost effective and efficient choice that from cellular phone in our hands to the computers, televisions, radios and a different controller, PLL is everywhere.
Rajib Imran +2 more
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2018 IEEE Custom Integrated Circuits Conference (CICC), 2018
▪ Digital PLLs exploit CMOS scaling and allow accurate cancellation of fractional spurs and automatic bandwidth control ▪ In Bang-Bang DPLLs assisted by DTC, performance is only limited by DCO and DTC resolution ▪ Bang-Bang DPLLs assisted by DTC allow same phase-noise performance and fractionalspur level as standard DPLLs at much lower power ...
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▪ Digital PLLs exploit CMOS scaling and allow accurate cancellation of fractional spurs and automatic bandwidth control ▪ In Bang-Bang DPLLs assisted by DTC, performance is only limited by DCO and DTC resolution ▪ Bang-Bang DPLLs assisted by DTC allow same phase-noise performance and fractionalspur level as standard DPLLs at much lower power ...
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New dual digital phase‐locked loop
Electronics and Communications in Japan (Part I: Communications), 1986AbstractIn the phase‐locked loop (PLL), the following mehods are used to eliminate the steady‐state phase error produced by the input signal with frequency off‐set: (1) the perfect integrator is used as the loop filter, realizing the perfect second‐order PLL; (2) the dual phase‐locked loop (DuLL) is constructed by combining two first‐order PLL's ...
Shoichiro Yamasaki +2 more
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Quasi-Optimum Digital Phase-Locked Loops
IEEE Transactions on Communications, 1973Quasi-optimum digital phase-locked loops (DPLL) are derived utilizing nonlinear estimation theory. Nonlinear approximations are employed to yield realizable loop structures. Baseband equivalent loop gains are derived, which, under high signal-to-noise ratio conditions may be calculated off line.
D. Polk, S. Gupta
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CMOS High-Resolution All-Digital Phase-Locked Loop
2003 46th Midwest Symposium on Circuits and Systems, 2006The core of an all-digital phase locked-loop (ADPLL) is composed of a high resolution digital controlled oscillator (DCO) circuit operating in a wide frequency range, a phase-frequency detector (PFD) and an up/down binary counter. The ADPLL can be reused in many system-on-chip (SoC) applications by a proper setting of the DCO and the PFD.
E. Mokhtari, M. Sawan
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Quantization Effects in All-Digital Phase-Locked Loops
IEEE Transactions on Circuits and Systems II: Express Briefs, 2007This brief analyzes the impact of the quantization noise sources in all-digital phase-locked loops (ADPLLs), recently employed as frequency synthesizers. In general, the in-band phase noise is not only caused by the phase quantization of the time-to-digital converter, but also by the frequency quantization of the digitally controlled oscillator (DCO ...
P. Madoglio +4 more
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Advanced digital phase-locked loops
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013Analog PLLs do not scale down as process and are not amenable to noise-cancellation and other calibration algorithms; Digital PLLs exploit CMOS scaling and allow for simple, accurate implementation of digiphase and two-point modulation; Typically, DPLLs require TDCs with tight resolution to achieve low phase noise and fractional-spur level, which ...
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