Results 1 to 10 of about 41,111,468 (182)
Self-organized synchronization of digital phase-locked loops with delayed coupling in theory and experiment. [PDF]
PLoS ONE, 2017 Self-organized synchronization occurs in a variety of natural and technical systems but has so far only attracted limited attention as an engineering principle. In distributed electronic systems, such as antenna arrays and multi-core processors, a common
Lucas Wetzel +5 more
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A Review on Micro-Watts All-Digital Frequency Synthesizers [PDF]
MicromachinesThis paper reviews recent developments in highly integrated all-digital frequency synthesizers suitable to deploy in low-power internet-of-things (IoT) applications.
Venkadasamy Navaneethan +4 more
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10−21-Level optical frequency dissemination over 2067 km of noise-loaded field-deployed fiber network [PDF]
Light: Science & ApplicationsAchieving ultra-stable optical frequency dissemination over long-haul fiber networks is essential for numerous applications. Although optical frequency transfer systems based on optical phase-locked loops (OPLLs) have achieved unprecedented stability ...
Fa-Xi Chen +11 more
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A Novel MSPLL-Based Method for Frequency Synthesis in Hydrogen MASER [PDF]
SensorsFrequency synthesis is an important aspect of an atomic clock. It is also imperative that the synthesized frequency exhibits good short term stability or, in other words, exhibits good phase noise.
Dipika Simariya +7 more
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L-SHADE-Optimized Active Disturbance Rejection for Sensorless PMSM Drives Under Complex Uncertainties [PDF]
SensorsSensorless permanent magnet synchronous motor (PMSM) drives rely on accurate rotor electrical angle and speed estimation, vulnerable to noisy currents, quantization, and sensor biases.
Xiaoqing Chen +3 more
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Low Power Clock Generator Design With CMOS Signaling
IEEE Open Journal of the Solid-State Circuits Society, 2021 The requirements for computing with higher energy efficiency in the datacenter and for longer battery life in laptop computers, cell phones, and other IoT devices while increasing performance with higher frequency and more cores, drive the needs for more
Yongping Fan, Ian A. Young
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All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops
IET Circuits, Devices and Systems, 2021 Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of ...
Lanhua Xia, Jifei Tang
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A Single-Event-Hardened Scheme of Phase-Locked Loop Microsystems for Aerospace Applications
Micromachines, 2022 In order to improve the ability of the phase-locked loop (PLL) microsystem applied in the aerospace environment to suppress the irradiation effect, this study presents an efficient charge pump hardened scheme by using the radiation-hardened-by-design ...
Qi Xiang, Hongxia Liu, Yulun Zhou
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Chimeras in digital phase-locked loops [PDF]
Chaos: An Interdisciplinary Journal of Nonlinear Science, 2019 Digital phase-locked loops (DPLLs) are nonlinear feedback-controlled systems that are widely used in electronic communication and signal processing applications. In most of the applications, they work in coupled mode; however, a vast amount of the studies on DPLLs concentrate on the dynamics of a single isolated unit.
Bishwajit Paul, Tanmoy Banerjee
openaire +4 more sources
Energies, 2017 The control system of a doubly-fed adjustable-speed pumped-storage hydropower plant needs phase-locked loops (PLLs) to obtain the phase angle of grid voltage.
Wei Luo, Jianguo Jiang, He Liu
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