Results 11 to 20 of about 2,220 (245)
Chimeras in digital phase-locked loops [PDF]
Digital phase-locked loops (DPLLs) are nonlinear feedback-controlled systems that are widely used in electronic communication and signal processing applications. In most of the applications, they work in coupled mode; however, a vast amount of the studies on DPLLs concentrate on the dynamics of a single isolated unit.
Bishwajit Paul, Tanmoy Banerjee
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The control system of a doubly-fed adjustable-speed pumped-storage hydropower plant needs phase-locked loops (PLLs) to obtain the phase angle of grid voltage.
Wei Luo, Jianguo Jiang, He Liu
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Non-linear behaviour of charge-pump phase-locked loops [PDF]
The analysis of the mixed analogue and digital structure of charge-pump phase-locked loops (CP-PLL) is a challenge in modelling and simulation. In most cases the system is designed and characterized using its continuous linear model or its discrete ...
C. Wiegand, C. Hedayat, U. Hilleringmann
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A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs
This paper proposes a resolution control loop that runs in background to control the time resolution of a mid-rise Time to Digital Converter (TDC) used as a phase detector in All-Digital Phase Locked Loops (ADPLLs).
Abdelrahman Habib +2 more
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Extended Lock Range Zero-Crossing Digital Phase-Locked Loop with Time Delay
The input frequency limit of the conventional zero-crossing digital phase-locked loop (ZCDPLL) is due to the operating time of the digital circuitry inside the feedback loop.
Nasir Qassim
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Understanding of the Coherent Demodulation with Phase-Locked Loop
The phase-locked loop (PLL) technology is a very important technology in the communication field. With the development of electronic technology toward digitalization, the phase-locked processing of signal needs to be realized in digital way.
Zhai Bingcong
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Design of novel hybrid - digitally controlled oscillator for ADPLL
Digitally Controlled Oscillators (DCOs) are an integral part of All Digital Phase Locked Loops (ADPLLs). It is used to generate output frequency corresponding to the applied digital input.
Mohd Ziauddin Jahangir +1 more
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A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA
In this paper, a digital-to-time converter (DTC) based on the three delay lines (3D) Vernier principle is proposed and implemented with field programmable gate arrays (FPGAs).
Chenggang Yan, Chen Hu, Jianhui Wu
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The interconnection of new generating and storing devices to the power grid imposes the necessity of synchronizing, so the power flow can be manipulated and distributed.
Luis Ibarra +3 more
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Modelling of 3-Phase p-q Theory-Based Dynamic Load for Real-Time Simulation
This article proposes a new method of modelling dynamic loads based on instantaneous p-q theory, to be employed in large powers system network simulations in a digital real-time environment.
Karthik Rajashekaraiah +3 more
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