Techniques for automatic on chip closed loop transfer function monitoring for embedded charge pump phase locked loops. [PDF]
, 2003 Charge Pump Phase locked loops are used in a variety of applications, including on chip clock synthesis, symbol timing recovery for serial data streams, and generation of frequency agile high frequency carrier signals.
Burbidge, Martin J. +5 more
core +5 more sources
Simple digital only test approach for embedded charge-pump phase-locked loops. [PDF]
, 2001 Techniques for a simple automated test approach for high performance fully embedded charge-pump phase-locked loops (CP-PLLs) are explained. The test approach is focused towards non-invasive high volume production testing of PLLs using digital only ...
Burbidge, M., Richardson, Andrew M. D.
core +5 more sources
Phase Locked Loop Test Methodology [PDF]
, 2008 Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based.
Burbidge, Martin, Richardson, Andrew
core +4 more sources
Phase jitter dynamics of first-order digital phase-locked loops with frequency-modulated input [PDF]
, 2008 IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, USA, 18-21 May 2008Inherent to digital phase-locked loops is frequency quantization in the number-controlled oscillator which prevents the loop from locking exactly onto its reference
Tertinek, Stefan +5 more
core +1 more source
Non-linear behaviour of charge-pump phase-locked loops [PDF]
Advances in Radio Science, 2010 The analysis of the mixed analogue and digital structure of charge-pump phase-locked loops (CP-PLL) is a challenge in modelling and simulation. In most cases the system is designed and characterized using its continuous linear model or its discrete ...
C. Wiegand, C. Hedayat, U. Hilleringmann
doaj +1 more source
A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs
IEEE Access, 2023 This paper proposes a resolution control loop that runs in background to control the time resolution of a mid-rise Time to Digital Converter (TDC) used as a phase detector in All-Digital Phase Locked Loops (ADPLLs).
Abdelrahman Habib +2 more
doaj +1 more source
Output-jitter performance of second-order digital bang-bang phase-locked loops with nonaccumulative reference clock jitter [PDF]
, 2011 Bang-bang phase-locked loops (BBPLLs) are inherently nonlinear systems due to the binary phase detector (BPD). While they are typically used for clock and data recovery, the ongoing trend toward digital loop implementations has resulted in several ...
Tertinek, Stefan +3 more
core +1 more source
Extended Lock Range Zero-Crossing Digital Phase-Locked Loop with Time Delay
EURASIP Journal on Wireless Communications and Networking, 2005 The input frequency limit of the conventional zero-crossing digital phase-locked loop (ZCDPLL) is due to the operating time of the digital circuitry inside the feedback loop.
Nasir Qassim
doaj +2 more sources
Understanding of the Coherent Demodulation with Phase-Locked Loop
MATEC Web of Conferences, 2018 The phase-locked loop (PLL) technology is a very important technology in the communication field. With the development of electronic technology toward digitalization, the phase-locked processing of signal needs to be realized in digital way.
Zhai Bingcong
doaj +1 more source
A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA
Applied Sciences, 2019 In this paper, a digital-to-time converter (DTC) based on the three delay lines (3D) Vernier principle is proposed and implemented with field programmable gate arrays (FPGAs).
Chenggang Yan, Chen Hu, Jianhui Wu
doaj +1 more source