Results 41 to 50 of about 41,111,468 (182)
Complexity, 2020 Based on the step function and signum function, a chaotic system which can generate multiscroll chaotic attractors with arrangement of saddle-shapes is proposed and the stability of its equilibrium points is analyzed.
Faqiang Wang, Yufang Xiao
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Digitalized analog integrated circuits
Fundamental ResearchDigital integrated circuits have significantly benefited from technology scaling down, while conventional analog integrated circuits suffer from more design constraints.
Zhangming Zhu, Shubin Liu
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Phase noise and jitter modeling for fractional-N PLLs [PDF]
Advances in Radio Science, 2007 We present an analytical phase noise model for fractional-N phase-locked loops (PLL) with emphasis on integrated RF synthesizers in the GHz range. The noise of the crystal reference, the voltage-controlled oscillator (VCO), the loop filter, the charge ...
S. A. Osmany +3 more
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International Journal of Reconfigurable Computing, 2014 This paper presents an efficient all digital carrier recovery loop (ADCRL) for quadrature phase shift keying (QPSK). The ADCRL combines classic closed-loop carrier recovery circuit, all digital Costas loop (ADCOL), with frequency feedward loop, maximum ...
Kaiyu Wang +4 more
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Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration
Journal of Electrical and Computer Engineering, 2013 Phase-locked loops (PLLs) employing LC-based voltage-controlled oscillators (LC VCOs) are attractive in low-jitter multigigahertz applications. However, inductors occupy large silicon area, and moreover dense integration of multiple LC VCOs presents the ...
Reza Molavi +3 more
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Design Considerations for Integrated Radar Chirp Synthesizers
IEEE Access, 2019 Phase-locked loops (PLLs) effectively generate frequency chirps for frequency-modulated continuous-wave (FMCW) radar and are ideal for integrated circuit implementations.
Daniel Weyer +6 more
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Transient and Stability Analysis of Voltage Switch Charge Pump PLL
Mehran University Research Journal of Engineering and TechnologyPhase-Locked Loops (PLLs) are widely used in modern communication, sensing, and digital systems for frequency synthesis, clock generation, and synchronization. Understanding their transient behavior and stability is essential for achieving fast, accurate,
Shazia Feroz, Ehsan Ali, Darshna Narwani
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Designing a time-to-digital converter using quantum-dot cellular automata nanotechnology
Scientific ReportsAs a nanoscale computing paradigm, quantum-dot cellular automata (QCA) technology demonstrates significant advantages over conventional CMOS implementations, including improved device density, minimized power dissipation, and increased operational speed.
Shahram Modanlou, Mohammad Gholami
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Experimental research of transient processes in firmware digital phase-locked loop
Tekhnologiya i Konstruirovanie v Elektronnoi Apparature, 2016 This article considers the experimental research of transient processes that occur in digital phase-locked loops (DPLL) after closing the feedback loop. Firmware implementation of DPLL device was made for this purpose.
А. П. Бондарев +1 more
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Mutually Coupled Time-to-Digital Converters (TDCs) for Direct Time-of-Flight (dTOF) Image Sensors ‡
Sensors, 2018 Direct time-of-flight (dTOF) image sensors require accurate and robust timing references for precise depth calculation. On-chip timing references are well-known and understood, but for imaging systems where several thousands of pixels require seamless ...
Augusto Ronchini Ximenes +2 more
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